Instuction set
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1 Instuction set In PIC16 series, RISC(Reduced Instruction Set Computer) is adopted and the number of the instructions to use is 35 kinds. When clicking the mnemonic of each instruction, you can jump to the instruction specification. The terminology explanation Mnemonic : The assembler language which made an operation code plain Operands : The specification part except the operation code MSb LSb Flag d : Most Significant bit : Least Significant bit : The field of the STAUS register : Bit in each instruction that determines the placement of the result 1/0 : f gets answer/w gets answer W f : bi- operand arithmetic operations always involve W (the accumulator) : General Purpose Reg 7 bits of the instruction RP0/RP1 of status reg 9 bits : address 512 memory locations literal k address data : pass a value as part of the instruction either an address or data : literal is 11 bits 2048 address out of 8192 total program space : literal is 8 bits (data width for PIC16) REGISTER 2-1: STATUS: STATUS REGISTER R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC (1) C (1) bit 7 bit 0 Mnemonic Operands Operation explanation Instruction code Flag Byte-oriented file register operations ADDWF f, d Add W and f C, DC, Z ANDWF f, d AND W with f Z CLRF f Clear f Z CLRW - Clear W Z COMF f, d Complement f Z DECF f, d Decrement f Z
2 DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f Z INCFSZ f, d Increment f, Skip if 0 IORWF f, d Inclusive OR W with f Z MOVF f, d Move f Z MOVWF f Move W to f NOP - No Operation RLF f, d Rotate Left f through Carry C RRF f, d Rotate Right f through Carry C SUBWF f, d Subtract W from f C, DC, Z SWAPF f, d Swap nibbles in f XORWF f, d Exclusive OR W with f Z Bit-oriented file register operations BCF f, b Bit Clear f BSF f, b Bit Set f BTFSC f, b Bit Test f, Skip if Clear BTFSS f, b Bit Test f, Skip if Set Literal and control operations ADDLW k Add literal and W C, DC, Z ANDLW k AND literal with W Z
3 CALL k Call subroutine CLRWDT - Clear Watchdog Timer GOTO k Go to address IORLW k Inclusive OR literal with W Z MOVLW k Move literal to W RETFIE - Return from interrupt RETLW k Return with literal in W RETURN - Return from Subroutine SLEEP - Go into stanby mode SUBLW k Subtract W from literal C, DC, Z XORLW k Exclusive OR literal with W Z Mnemonic C? Z? Description 12 BITS for instructions 2Bits 14 total bits 12 for instruction 2 for status opcode 5b Miscellaneous instructions NOP No operation (MOVW 0,W) OPTION Copy W to OPTION register SLEEP Go into standby mode CLRWDT Restart watchdog timer f TRIS f Copy W to tri-state register (f = 1, 2 or 3) 0 0 opcode 4b d register 5b ALU operations: dest OP(f,W)
4 f MOVWF f dest W d f CLR f,d Z dest 0, usually written CLRW or CLRF f d f SUBWF f,d C Z dest f W (dest f+~w+1) d f DECF f,d Z dest f d f IORWF f,d Z dest f W, logical inclusive or d f ANDWF f,d Z dest f & W, logical and d f XORWF f,d Z dest f ^ W, logical exclusive or d f ADDWF f,d C Z dest f+w d f MOVF f,d Z dest f d f COMF f,d Z dest ~f, bitwise complement d f INCF f,d Z dest f d f DECFSZ f,d dest f 1, then skip if zero d f RRF f,d C dest CARRY<<7 f>>1, rotate right through carry d f RLF f,d C dest F<<1 CARRY, rotate left through carry d f SWAPF f,d dest f<<4 f>>4, swap nibbles d f INCFSZ f,d dest f+1, then skip if zero 0 1 op bit register Bit operations bit f BCF f,b Clear bit b of f bit f BSF f,b Set bit b of f bit f BTFSC f,b Skip if bit b of f is clear bit f BTFSS f,b Skip if bit b of f is set 1 0 op k Control transfers k RETLW k Set W k, then return from subroutine k CALL k Call subroutine, 8-bit address k k GOTO k Jump to 9-bit address k[10] 1 1 op 8-bit immediate Operations with W and 8-bit literal: W OP(k,W) k MOVLW k W k k IORLW k Z W k W, bitwise logical or k ANDLW k Z W k & W, bitwise and k XORLW k Z W k ^ W, bitwise exclusive or Mnemonic C? Z? Description Link between mikroc and these instructions: (see phystu/class 0f 2012/Matt Chamberlin/mikroC_2/xxx projects and code) You can directly execute an insruction asm assembly_instruction; Or a block of assembly asm { block of assembly instructions }
5 mikroc PRO for PIC has additional set of keywords that do not belong to the ANSI standard C language keywords: ("Keywords" are words that have special meaning to the C compiler e.g. instruction such as int, float) code data rx (This memory specifier variable stored in the Rx space (Register file).) at sbit bit sfr (This mem spec - with (rx, data) - access spec func reg. - maintain same identifier in C& assembly.) sfr keyword ids variables as register references and allows bit manipulation (ids variables as specific bits in a register (special function register (SFR)). sbit name = sfr-name ^ bit-position; sbit name = sfr-address ^ bit-position; sbit name = sbit-address; ( sfr PSW = 0xFF10; //PSW refers to a regiser with an absolute address sbit USR0 = PSW ^ 6; // USR0 refers to bit 6 in PSW sfr / sbit signifies both a data- type and storage class, they are used to describe the special function registers and special bit variables of a (Associating identifiers with objects requires each identifier to have at least two attributes: storage class and type. Storge classes are used to define the scope (visability) and life time of variables. static is a storage class that makes the variable constant. extern is a storage class that makes variables global.) A storage class dictates the location (data segment, register, heap, or stack) of object and its duration or lifetime. All PIC SFR registers and their bits are implicitly declared as global variables. These identifiers have an external linkage, and are visible in the entire project. When creating a project, the mikroc PRO for PIC will include an appropriate (*) file from defs folder, containing declarations of available SFR registers and constants.//// Special function registers (SFRs) sfr unsigned short volatile INDF absolute 0x0000; sfr unsigned short volatile TMR0 absolute 0x0001; sfr unsigned short volatile PCL absolute 0x0002; sfr unsigned short volatile STATUS absolute 0x0003; sfr unsigned short FSR absolute 0x0004; register unsigned short *FSRPTR absolute 0x0004; sfr unsigned short volatile PCLATH absolute 0x000A; sfr unsigned short volatile INTCON absolute 0x000B; storage-class [type-qualifier] type var1 [=init1]
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