Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis

Transcription

1 Synthesis of Language Constructs 1

2 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1 are implemented as wires supply0, supply1 are implemented as constants wand, wor are implemented as gates The strength of nets is ignored 2

3 Register Variables Integers default: 32-bit registers size may be reduced in optimization process constants should be declared having a fixed size to reduce the size of the hardware register real, time and realtime variables are not supported 3

4 Memories (Arrays) Multiple copies of a multiple-bit register May not be recognized by some synthesis tools Example: 4

5 Synthesis Result Synthesis tools will implement each memory bit with a latch/ff In general memories are external to the description that is to be synthesized 5

6 x and z Only allowable uses of x in casex casez defaults of conditionals (such as if, case, and? :) Only allowable uses of z in constructs implying a 3-state output Don t cares x assigned to wire or reg by a UDP x as a default assignment in a conditional statment Three-state devices z assigned to wire or reg as the default outcome for a conditional statement 6

7 Arithmetic Operators A variety of possible implementations adder ripple carry or carry lookahead * and / may not be implemented efficiently as combinational logic special cases: use of left and right shift for * and / when one operand is a power of 2; use of part select for % when the divisor is a power of 2 7

8 Example r[4:0] = - a[3:0] - is done by 1 s complement + 1 8

9 Shift Operators The shift amount or the number of bits storing the shift amount must be a constant Within a behavior, they are implemented with shift registers and multiplexers implemented from low-level logic gates, and not necessarily mapped into a library cell of a shift register 9

10 Example 10

11 Basic Structure for LSB 11

12 Synthesis Result 12

13 Relational and Identity Operators Relational operators (<, >, >=, <=) implemented with combinational logic implemented with adder/subtractor A >= B if the sign bit of A-B is 0, and A<B otherwise Identity operators (==,!=, ===,!==) implemented with combinational logic implemented with gates (when used to support data select in a conditional statement) 13

14 Example 14

15 Example module identity_if_4bit (data_out, data_a, data_b, data_c, data_d, sel); input [3:0] data_a, data_b, data_c, data_d; input [1:0] sel; 15

16 Synthesis Result Use gates to implement 16

17 Another Synthesis Result Use 4-channel mux to implement 17

18 Reduction, Bitwise, Logical Operators Translated to Boolean equations and mapped to physical gates Example: 18

19 Conditional Operators Synthesized into muxes or gates that implement muxes Example: 19

20 Concatenation Operators Supported by synthesis tools in general Equivalent to a logical bus with no functionality of its own 20

21 Grouping of Operators 21

22 Continuous Assignments Translated to Boolean equations which are then optimized and synthesized into combinational gates No structural feedback allowed 22

23 Procedural Assignments = operator PCAs assign deassign: vendor dependent force release: not supported 23

24 Expression Substitution Synthesis tools perform expression substitution to get the outcome of a sequence of procedural (blocking) assignments Example: Three additions should be enough in the dataflow graph. dataflow structure 24

25 Equivalent Behavior 25

26 Synthesis Result 26

27 Non-Blocking Assignments 27

28 Variation module pipe1_alt (data, rega, regb, regc, clk, reset); input [1:0] data; input clk, reset; rega is from the previous cycle, not the current one! Synthesis result is different from that of pipe1 28

29 Another Variation expression substitution rega = data; regb = data + 1; regc = data equivalent to rega <= data; regb <= data +1; regc <= data ; 29

30 case and if Example: (note that unused input s2 is retained) 30

31 Resets An asynchronous reset is typically modeled within an event control expression detecting the synchronizing signal of a behavior The assign deassign construct allows a separate behavior for an asynchronous reset simulation efficient, but not universally supported If the library components selected by a synthesis tool have sets/resets that do not appear in the Verilog code, their sets/resets will be tied to power/ground 31

32 Delay Controls Not advisable to include delay controls in a behavior that is to be synthesized Delay controls that are shorter than a clock cycle will be ignored Some synthesis tools will place a procedural assignment in succeeding clock cycles if the delay associated with the assignment is longer than a clock cycle 32

33 Event Controls For a cyclic behavior that is to model combinational logic, if some input variable is not in the event control expression or the RHS of a procedural continuous assignment, a latch will be inferred. If there is an edge qualifier, synchronous logic is implied, otherwise a latch or combinational logic is implied. 33

34 Event Controls For an event control expression with posedge (negedge) reset it has only one clock edge it can have any number of other signals that are asynchronous control signals and accompanied individually by an edge qualifier In an event control expression, no signal may be qualified by both posedge and negedge 34

35 Event Controls The statement associated with an event control expression should be a conditional branch statement (i.e., if, or? :) The branches of the conditional statement are separated into synchronous and asynchronous parts with only one synchronous branch A branch not dependent upon a signal in the event control expression is assumed synchronous The synchronous branch must be the last branch in the statement asynchronous control signals have priority over the synchronous signal 35

36 Example (posedge x or posedge y or posedge z) begin if (x) a <= 0; else if (y) a <= 1; // z is not mentioned here, and is assumed synchronous else a <= b & c; 36

37 Multiple Event Controls Can be used in implicit FSMs Distribute activity over successive clock cycles (posedge clk) (posedge clk) Can not mix posedge clk and negedge clk in the same behavior for synthesis 37

38 wait If supported, the condition for delay must include one value generated by a separate concurrent behavior or continuous assignment The condition must be held in the true state for at least one clock cycle When the condition is generated in a behavior other than the one the wait construct appears, the same clock should be in both behaviors 38

39 Named Events May not be supported Two behaviors to accommodate generation and triggering Communicating behaviors must have the same clock, or different clocks with the same period Communicating behaviors can use the same or different edges of the same clock If the same edge is used, the generation (->) behavior must have a delay control of less than one clock period inserted before the generation statement e.g., (posedge clk) begin statement_1; statement_2; #1 -> event_b_is_triggered; end event_b_is_triggered //edge (posedge clk) begin statement_3; statement_4; end 39

40 Multi-Cycle Operations A multi-cycle operation requires more than one clock cycle to complete Example: module m_cycle (result, a, b, c, clk); input a, b, c, clk; output [1:0] result; reg [1:0] result, temp; (posedge clk) begin temp = a + (posedge clk) result = temp + c; end endmodule 40

41 Loops A loop is static (data-independent) if the number of iterations can be determined by the compiler (i.e., the number of iterations is fixed) Loop types static without internal timing controls combinational logic static with internal timing controls sequential logic non-static without internal timing controls not synthesizable non-static with internal timing controls sequential logic 41

42 Static Loops without Internal Timing Controls Combinational logic results from loop unrolling Example: module for_and_loop_comb (out, a, b); input [3:0] a, b; output [3:0] out; reg [2:0] i; reg [3:0] out; (a or b) begin for (i = 0; i < 4; i = i + 1) out[i] = a[i] & b[i]; end endmodule For registered outputs, replace a or b with posedge clk to get another module for_and_loop_reg 42

43 Synthesis Results result form for_and_loop_comb result from for_and_loop_reg 43

44 Example 44

45 Results 45

46 Static Loops with Internal Timing Controls If a static loop contains an internal edge-sensitive event control expression, then the computational activity of the loop is synchronized and distributed over one or more clock cycles Example: 46

47 Simulation Results 47

48 Non-Static Loops without Internal Timing Controls The number of iterations in the loop is determined by a variable modified within the loop Can be simulated, but not synthesized Essentially an iterative combinational circuit of data dependent size 48

49 Example 49

50 Simulation Results 50

51 Non-Static Loops with Internal Timing Controls Due to internal timing controls, the activity of the loop is distributed over multiple cycles with the number of cycles determined by a variable modified within the loop Example: 51

52 Simulation Results 52

53 FSM Replacements for Loops Not all loop constructs are supported by vendors Can always implement a loop using an FSM Example: add add 0 done <= 1 1 data_ready 0 53

54 Simulation Results 54

55 fork join Describe parallel threads of activity Not supported, or restricted not to contain event and delay controls that are equal to or longer than a clock cycle all threads complete in one clock cycle Use non-blocking assignments instead to get parallelism 55

56 disable A disable statement is to disable a function, task, or named block Two kinds of disables: external disable: infers sequential logic internal disable: models the reset condition in an implicit FSM, or the external interrupt of a machine 56

57 Example 57

58 User-Defined Tasks Synthesis tools expand a task inline A task that is to be synthesized may not contain inout ports A task containing no event controls will synthesize to combinational logic 58

59 Example 59

60 User-Defined Functions Functions are expanded at the site of their call A function will synthesize to combinational logic Incompletely specified case and if statements are not allowed within a function 60

61 Example 61

62 Specify Blocks and Compiler Directives specify endspecify ignored Compiler directives synthesized 62