Lecture 5:8086 Outline: 1. introduction 2. execution unit 3. bus interface unit

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1 Lecture 5:8086 Outline: 1. introduction 2. execution unit 3. bus interface unit 1

2 1. introduction The internal function of 8086 processor are partitioned logically into processing units,bus Interface Unit(BIU) and Execution Unit (EU).general block diagram of 8086 processor is shown in figure (1). Figure 1: general block diagram of The Execution unit EU is used mainly to execute instructions. It contains a circuit called the arithmetic and logic unit (ALU). T he data for operations are stored in circuit called Registers. The EU has eight registers for storing data; their names are AX, BX, CX, DX, SI, DI, BP, SP and FLAGS register. The EU accepts instructions and data that have been fetched by the 2

3 BIU and then processes the information. Data processed by the EU can be transmitted to the memory or peripheral devices through the BIU. EU has no direct connection with the outside world and relies solely on the BIU to feed it with instruction and data. It is here that instructions are received, decoded, and executed from the instruction queue portion of BIU. The instructions are taken from the top of the instruction queue on the first-in, first-out, or FIFO, basis. 2.1 ALU The ALU is the calculator part of the execution unit. It consists of electronic circuitry that performs arithmetic operations or logical operations on the binary represented electrical signals. The control system for the execution unit can also be thought of as part of ALU. It provides a path for the flow of instructions into the ALU, the general registers, and the flag register 2.2 flag register A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations of the EU. The Flag Register is a special register associated with the ALU. A 16-bit flag register in the EU contains nine active flags. Fig.ure (2) shows the location of the nine flags in the flag register 3

4 Figure 2: flag register Six flags are status flags- AF, CF, OF, SF, PF and ZF. The remaining three flags are control flags -DF,IF, and TF. Flags are described as: AF (auxiliary flag): If this flag is set, there has been a carry out or borrow of the 4least significant bits. This flag is used during decimal arithmetic instructions. CF (carry flag): If this flag is set, there has been a carry out or overflow of the mostsignificant bit. It is used by instructions that add and subtract multi byte numbers. OF (overflow flag): If this flag is set, an arithmetic overflow has occurred; that is, a significant digit has been lost because the size of the result exceeded the capacity of its destination location. SF (sign flag): Since negative binary numbers are represented in the 8086/8088 in standard 2s 4

5 complement notation. SF indicates the sign of the result (0 = positive, 1= negative). PF (party flag): If this flag is set, the result has even parity, an even number of 1s.This flag can be used to check for transmission errors. ZF (zero flag): If this flag is set, the result of the operation is 0. DF (direction flag): Setting DF causes string instructions to auto-decrement (countdown); that is, to process strings from the high address to the low address, or from right to left. Clearing DF causes string instructions to aut o- increment (count up), or process strings from left to right. IF (interrupt-enable flag): setting IF allows the CPU to recognize external (maskable) interrupt requests. Clearing IF disables these interrupts. IF has no effect on either nonmaskable external or internally generated interrupt. TF (trap flag): Setting TF puts the processor into single - step mode for debugging. In this mode the processor automatically generates an internal interrupt after each instruction, allowing a program to be inspected as it executes instruction by instruction. 2.3 General Purpose Registers EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL, DH and DL. These registers are a set of data registers, which are used to hold intermediate results. The H represents the high- order or most-significant byte and the L represents the low-order or least-significant byte. Each of these registers may be used separately as 8 -bit storage areas 5

6 or combined to form one 16-bit (one word) storage area. The5 acceptable register pairs are AH and AL, BH and BL, CH and CL and DH and DL. The AH-AL pair is referred to as the AX register, the BH-BL pair is referred to as the BX register, the CH-CL pair is referred to as the CX register, and the DH-DL pair is referred to as the DX register. The AL register is also called as the accumulator.for 16-bit operations, AX is called the accumulator. 2.4 Stack Pointer Register A Stack, is a section of memory set aside to store addresses and data while a subprogram is being executed. An entire 64 K bytes segment is set aside as stack in 8086 processor. The upper 16 bits of the starting address for this segment is kept in the stack segment register. The Stack Pointer (SP) register contain the 16-bit offset from the start of the segment to the memory location where a word was most recently stored on the Stack. The memory location where a word was most recently stored is called the top of Stack. The physical address for a stack read or for a stack write is produced by adding the contents of the stack pointer register to the segment base address in SS. To do this the contents of the Stack segment register are shifted four bit positions left and the contents of SP are added to the shifted result. 3. The Bus Interface Unit The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory. In other words 6

7 the BIU handles all transfers of data and addresses on the buses for the execution unit. The BIU can be thought of as three functional blocks; Bus control Instruction queue and Address control 3.1. But control The bus-control unit performs the bus operations for the processor. It fetches and transmits instructions, data and control signals between processor and the other devices of the system 3.2. Instruction Queue The instruction queue is used as a temporary memory storage area for data instructions that are to be executed by the EU. The BIU, through the bus-control unit, prefetches instructions and stores them in the instruction queue. This allows execution unit to perform its calculations at maximum efficiency because the BIU and EU essentially operate independently, the BIU concentrates on loading instructions into the instruction queue. This usually takes more time to do than the calculations performed by the execution unit. In effect, the BIU and the EU work in parallel. The instruction queue is a first-in, first out (FIFO) memory. This means that the first instruction loaded into the instruction queue by the bus control unit will be the first instruction to be used the ALU. 7

8 3.3 Instruction Pointer The Instruction Pointer (IP) is a 16- bit register that is used to point to, or tell the processor, the instruction to execute next. Therefore, the instruction pointer is used to control the sequence in which the program is executed. Each time the execution unit accepts an instruction, the instruction pointer, is incremented to point to the next instruction in the program. 3.4 Segment Registers There are four segment registers. They are the code segment (CS), the data segment (DS), the stack segment (SS), and the extra segment (ES). These registers are used to define a logical memory space or memory segment that is set aside for a particular function. The CS register points to the current cod e segment. Instructions are fetched from this segment. The DS register points to the current data segment. Program variables and data are held in this area. The SS register points to the current stack segment, stack operations are performed on locations in the SS segment. The ES register points to the current extra segment, which is also used for data storage. Each of the segment registers can be up to 64 kilo bytes long. Each segment is made up of an uninterrupted section of memory locations. Each segment can be addressed separately using the base address that is contained in its segment register. The base address is the starting address for that segment 8

8086 INTERNAL ARCHITECTURE

8086 INTERNAL ARCHITECTURE Segment 2 Intel 8086 Microprocessor The 8086 CPU is divided into two independent functional parts: a) The Bus interface unit (BIU) b) Execution Unit (EU) Dividing the work between