Topic #6. Processor Design

Transcription

1 Topic #6 Processor Design

2 Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between them.! To present the multiple-cycle implementation and to further develop the student's understanding of combinational and clocked sequential circuits and the relationship between them.! To introduce microprogramming. 2

3 How Are These Several Topics Related?! The performance of a computer is determined by (Topic #2): " count " Clock cycle time " Clock cycles per instruction (CPI)! The instruction count is determined by the compiler and the instruction set architecture (Topics #3, #4 and #5).! The clock cycle time and the CPI are determined by the implementation of the processor (Topic #6 -this topic). 3

4 A MIPS Subset Implementation! For illustration, we will study an implementation of a subset of the core MIPS instruction set: " Memory-reference instructions: lw, sw " Arithmetic-logical instructions: add, sub, and, or, slt " Branch and jump instructions: beq, j! s not included: " Integer instructions such as those for multiplication and division " Floating-point instructions 4

5 Steps to Execute MIPS s! Send the program counter (PC) to the memory location that contains the code and fetch the instruction from that memory location.! one or two registers, using fields of the instruction to select the registers to read. For the load word and store word instructions we need to read only one register, but most other instructions require that we read two registers.! Perform the operation required by the instruction using the ALU. Memory-reference instructions use the ALU for address calculation; arithmetic-logical instructions for operation execution; and branches for comparison.! Store the result in registers or memory locations, and change the value of the program counter in case of a branch instruction. 5

6 High-Level View of the MIPS Subset Implementation Data Register # PC Address Registers Register # ALU memory Register # Address Data memory Data 6

7 Sequential Logic Circuits! MIPS computers are designed using both combinational and sequential logic circuits.! Sequential logic circults are circuits whose output depends on both the current input and the value stored in memory (called state).! We will review: clocks and memory elements! Reference: Appendix B (B.4-B.5) of textbook 7

8 Clocks! A clock is a free-running signal with a fixed cycle time (or called clock period) or, equivalently, a fixed clock frequency (i.e., inverse of the cycle time).! Clocks are needed in sequential logic to decide when an element that contains state should be updated.! Edge-triggered clocking: " Design methodology for sequential logic circuits in which all state changes occur on a clock edge (rising edge or falling edge). Falling edge Clock period Rising edge 8

9 Clocked Systems! Clocked systems are also called synchronous systems.! Relationship among state elements and combinational logic blocks in a synchronous, sequential logic design: State element Combinational logic State element 2 Clock cycle State element Combinational logic 9

10 Memory Elements! All memory elements store state: the output from any memory element depends both on the current inputs and on the value that has been stored inside the memory element.! S-R latches (set-reset latches): " Unclocked memory elements built from a pair of crosscoupled NOR gates (i.e., OR gates with inverted outputs). R Q S _ Q

11 D Latches! Unlike S-R latches which are unclocked, D latches are clocked (i.e., state changes are triggered by a clock).! The output is equal to the value of the stored state inside it. C Q D D _ Q C Q! Operation: " When the clock C is asserted, the latch is open and the Q output immediately assumes the value of the D input.! Clocked latches are used to build flip-flops.

12 D Flip-Flops Flops! D flip-flops, like D latches, are clocked.! The outputs change only on the (rising or falling) clock edge.! D flip-flop with a falling-edge trigger: D D D latch C Q D C D latch Q _ Q Q _ Q D C C Q! Operation: " When the clock input C changes from asserted to deasserted, the Q output stores the value of the D input.! An array of D flip-flops can be used to build a register that can hold a multibit datum, such as a byte or word. 2

13 Register Files! A register file is a structure in the datapath consisting of a set of registers that can be read and written by supplying a register number to be accessed.! A register file can be implemented with a decoder for each read or write port and an array of registers built from D flipflops.! ing a register: " Input: a register number " Output: data contained in the specified register! Writing a register: " Inputs: a register number, the data to write, and a clock that controls the writing into the register 3

14 Example: A Register File with Two Ports and One Write Port! There are five inputs and two outputs.! The read ports can be implemented with a pair of multiplexors, each of which is as wide as the number of bits in the register file. register number register number 2 Register file Write register Write data Write data data 2 4

15 Implementation of Two Ports! To implement two read ports for a register file with n registers, we use two n-to- multiplexors, each of which is 32 bits wide. register number register number 2 Register Register Register n Register n M u x data! The read register number signal is used as the multiplexor selector signal. M u x data 2 5

16 Implementation of a Write Port! To implement the write port for a register file with n registers, we use an n-to- decoder to generate a signal that can be used to determine which register to write. Write C D Register Register number n-to- decoder n C D Register n Register data C Register n D C D Register n 6

17 SRAMs and DRAMs! Unlike registers which are small, fast memories inside the processor, larger amounts of memory are in the form of: " Static random access memories (SRAMs) " Dynamic random access memories (DRAMs)! SRAMs are usually used for relatively small memories (e.g., cache) while DRAMs are used for larger memories (e.g., main memory).! SRAMs are typically built using flip-flops while DRAMs are built using capacitors.! SRAMs are somewhat simpler in design than DRAMs, but they are also more expensive and less dense. 7

18 SRAMs! 256K x SRAM: " Length (i.e., number of addressable locations) = 256K " Width (i.e., number of bits per entry) = " 8 address lines, data input line, data output line Address 5 Chip select Output enable Write enable SRAM 32K 8 8 Dout[7 ] Din[7 ] 8! 32K x 8 SRAM: " 5 address lines, 8 data input lines, 8 data output lines 8

19 SRAMs! Large SRAMs cannot be built like register files using multiplexors, as a 64K-to- multiplexor (too large!) would be needed for a 64K x SRAM.! Instead, a shared output line, called bit line, is used so that multiple memory cells in the memory array can assert.! A multiplexor constructed from four three-state buffers: Select Data Select Data In In Enable Out Enable Out! A three-state buffer (or tristate buffer) is used to allow multiple sources to drive a single line. Select 2 Data 2 Select 3 Data 3 In In Enable Out Enable Out Output 9

20 A 4 x 2 SRAM Din[] Din[] Write enable D D C latch Enable Q D D C latch Enable Q 2-to-4 decoder D C D latch Q D C D latch Q Enable Enable Address D C D latch Q D C D latch Q Enable Enable 2 D C D latch Q D C D latch Q Enable Enable 3 Dout[] Dout[] 2

21 A 32K x 8 SRAM as an Array of 52 x 64 Arrays Address [4 6] 9-to-52 decoder SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM Address [5 ] 64 Mux Mux Mux Mux Mux Mux Mux Mux Dout7 Dout6 Dout5 Dout4 Dout3 Dout2 Dout Dout 2

22 DRAMs! The value kept in a cell is stored as a charge in a capacitor.! Only a single transistor is needed to access the stored charge (either to read the value or to overwrite the charge stored there), and hence DRAMs are much denser and cheaper per bit.! Since the charge is stored on a capacitor, it cannot be kept indefinitely but has to be refreshed periodically.! To refresh a cell, we read its content and then write it back.! Typically, refresh operations consume -2% of the active cycles, leaving 98-99% of the cycles available for reading and writing data. 22

23 A 4M x DRAM Built with a 248 x 248 Array Row decoder -to array Address[ ] Column latches Mux Dout 23

24 Synchronous RAMs! Synchronous SRAMs (SSRAMs) and synchronous DRAMs (SDRAMs)! The key capability provided by synchronous RAMs is the ability to transfer a burst of data from a series of sequential addresses within an array or row. The burst is defined by a starting address, supplied in the usual fashion, and a burst length.! The speed advantage of synchronous RAMs comes from the ability to transfer the bits in the burst without having to specify additional address bits. Instead, a clock is used to transfer the successive bits in the burst. 24

25 Building a Datapath! Some basic datapath elements: " memory: a memory unit that stores the instructions of a program and supplies an instruction given its address. " Program counter: a register that stores the address of the instruction being executed. " Adder: a unit that increments the program counter to the address of the next instruction. address PC Add Sum memory a. memory b. Program counter c. Adder 25

26 Building a Datapath! To execute any instruction, we first fetch the instruction from memory.! To prepare for executing the next instruction, we increment the program counter so that it points at the next instruction (4 bytes later). Add 4 PC address memory 26

27 Datapath for Arithmetic-Logical (R-Format) s register register 2 Registers Write register Write data RegWrite data data 2 3 ALU operation Zero ALU ALU result 27

28 Datapath for Load and Store (I-Format) s register register 2 Registers Write register Write data RegWrite data data 2 3 ALU operation Zero ALU ALU result Address Write data MemWrite Data memory data 6 Sign 32 extend Mem 28

29 Datapath for Branch (I-Format) s PC + 4 from instruction datapath Add Sum Branch target Shift left 2 register register 2 Registers Write register Write data RegWrite data data 2 6 Sign 32 extend 3 ALU ALU operation Zero To branch control logic 29

30 A Simple Single-Cycle Implementation! We have already built a datapath for each instruction separately. Now, we need to combine them into a single datapath, by devising ways to share some of the resources (e.g., ALU) among the different instructions instead of duplicating them.! This simple implementation is based on the (unrealistic) assumption that all instructions take just one clock cycle each to complete. " Implication: No datapath resource can be used more than once per instruction, so any element needed more than once must be duplicated. As a consequence, we need a memory for instructions separate from one for data. 3

31 Combined Datapath for R-Format R s and Memory s 4 Add PC address memory register register 2 Write register Write data RegWrite Registers data data 2 ALUSrc M u x 3 ALU operation Zero ALU ALU result Address Write data MemWrite data Data memory MemtoReg M u x 6 Sign 32 extend Mem 3

32 Combined Datapath for Different Classes PCSrc 4 Add Shift left 2 Add ALU result M u x PC address memory register register 2 Write register Write data Registers data data 2 RegWrite 6 Sign 32 extend ALUSrc M u x 3 ALU operation Zero ALU ALU result Address Write data Mem MemWrite data Data memory MemtoReg M u x 32

33 ALU Control! The control unit controls the whole operation of the datapath by generating appropriate control signals (e.g., write signals for state elements, selector inputs for multiplexors, ALU control inputs) for the proper operation of the datapath.! The ALU control is part of the main control unit.! Control input bits for ALU: ALU Control Input Function and or add subtract set on less than 33

34 ALU Control Input Bits! Inputs used by control unit to generate ALU control input bits: " ALUOp (2 bits) " Function code of instruction (6 bits) opcode ALUOp operation Function code Desired ALU action ALU control input Load word load word XXXXXX add Store word store word XXXXXX add Branch equal branch equal XXXXXX subtract R-type add add R-type subtract subtract R-type and and R-type or or R-type set on less than set on less than 34

35 Multiple Levels of Decoding! Level : Generation of ALUOp bits by main control unit - to be discussed later! Level 2: Generation of ALU control input bits from ALUOp bits and function code of instruction! Why multiple levels? " Using multiple levels of control can reduce the size of the main control unit, and may also potentially increase the speed of the control unit. " A common implementation technique. 35

36 Truth Table for ALU Control Block! The truth table contains many don't-care terms, which can lead to simplified hardware implementation. ALUOp ALUOp ALUOp F5 Function code F4 F3 F2 F F Operation X X X X X X X X X X X X X X X X X X X X X X X X X X X X 36

37 Hardware Implementation of ALU Control Block ALUOp ALUOp ALUOp ALU control block F3 Operation2 F (5 ) F2 F F Operation Operation Operation 37

38 Datapath with ALU Control PCSrc 4 Add RegWrite Shift left 2 Add ALU result M u x PC address [3 ] memory [25 2] [2 6] M u [5 ] x RegDst [5 ] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend ALUSrc M u x ALU control ALU Zero ALU result MemWrite Address Write data Data memory Mem data MemtoReg M u x [5 ] Destination register: R-format: rd field (bits 5-) lw: rt field (bits 2-6) ALUOp 38

39 Effects of Control Signals Signal name RegDst RegWrite ALUSrc PCSrc Mem MemWrite MemtoReg Effect when deasserted The register destination number for the Write register comes from the rt field (bits 2-6). None The second ALU operand comes from the second register file output ( data 2). The PC is replaced by the output of the adder that computes the value of PC + 4. None None The value fed to the register Write data input comes from the ALU. Effect when asserted The register destination number for the Write register comes from the rd field (bits 5-). The register on the Write register input is written with the value on the Write data input. The second ALU operand is the signextended, lower 6 bits of the instruction. The PC is replaced by the output of the adder that computes the branch target. Data memory contents designated by the address input are put on the data output. Data memory contents designated by the address input are replaced by the value on the Write data input. The value fed to the register Write data input comes from the data memory. 39

40 Setting of Control Signals! The 9 control signals (7 from the previous table + 2 from ALUOp) can be set based entirely on the 6-bit opcode, with the exception of PCSrc.! PCSrc control line: " Set if both conditions hold simultaneously: is beq. Zero output of ALU is true (i.e., the two source operands are equal). 4

41 Datapath with Control Unit 4 Add [3 26] Control RegDst Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add ALU result M u x PCSrc PC address memory [3 ] [25 2] [2 6] [5 ] M u x register data register 2 Registers Write data 2 register Write data M u x Zero ALU ALU result Address Write data Data memory data M u x [5 ] 6 Sign 32 extend ALU control [5 ] 4

42 Setting of Control Signals! Setting of control lines is completely determined by opcode: Reg- Dst ALU- Src Memto- Reg Reg- Write Mem- Mem- Write Branch ALUOp ALUOp R-format lw sw X X beq X X! Input to datapath control unit: Opcode in decimal Op5 Opcode in binary Op4 Op3 Op2 Op Op R-format lw 35 sw 43 beq 4 42

43 Truth Table for Datapath Control Unit Input or output Signal name R-format lw sw beq Op5 Op4 Inputs Op3 Op2 Op Op RegDst X X ALUSrc MemtoReg X X RegWrite Outputs Mem MemWrite Branch ALUOp ALUOp 43

44 Hardware Implementation of Datapath Control Unit Inputs Op5 Op4 Op3 Op2 Op Op R-format Iw sw beq Outputs RegDst ALUSrc MemtoReg RegWrite Mem MemWrite Branch ALUOp ALUOpO 44

45 Simple Datapath and Control Extended to Handle the Jump [25 ] Shift Jump address [3 ] left Add PC+4 [3 28] [3 26] Control RegDst Jump Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add result ALU M u x M u x PC address [3 ] memory [25 2] [2 6] [5 ] M u x register data register 2 Registers Write data 2 register Write data M u x Zero ALU ALU result Address Write data Data memory data M u x [5 ] 6 Sign 32 extend ALU control [5 ] 45

46 Problems with Single-Cycle Datapath Implementation! Every instruction takes one clock cycle (CPI = ). The clock cycle is determined by the longest possible path in the machine.! The longest path is for a load instruction which involves five functional units in series: instruction memory, register file, ALU, data memory, register file.! Even though each instruction takes just one clock cycle, the clock cycle is expected to be large and hence the overall performance is poor because many instructions cannot fully utilize the unnecessarily long clock cycle.! No sharing of hardware functional units is possible. 46

47 Different Classes class R-format Load word Store word Branch Jump Functional units used by the instruction class fetch Register access ALU Register access fetch Register access ALU Memory access Register access fetch Register access ALU Memory access fetch Register access ALU fetch E.g., memory units: 2 ns ALU: 2 ns register file (read/write): ns class memory Register read ALU operation Data memory Register write Total R-format ns Load word ns Store word ns Branch ns Jump 2 2 ns 47

48 Problems with Single-Cycle Datapath Implementation! Although a variable clock implementation would be faster, it is very difficult to implement a variable-speed clock.! The penalty for using a single-length clock cycle becomes more severe if we also consider other computationally demanding instructions such as multiplication and floating-point operations.! As a result, the best solution is to consider a shorter clock cycle (derived from the basic functional unit delays) and allow different instructions to require different numbers of clock cycles. 48

49 A Multicycle Implementation! The execution of each instruction is broken into a series of steps that correspond to the functional unit operations. Each step takes one clock cycle to complete.! A single functional unit can be used more than once per instruction, as long as it is used on different clock cycles. This sharing can help to reduce the amount of hardware required. In particular, " A single memory unit is used for both instructions and data. " There is a single ALU, rather than an ALU and two adders. " One or more registers are added after every major functional unit to hold the output of that unit until the value is used in a subsequent clock cycle. 49

50 High-Level View of the Multicycle Datapath PC Address Memory Data or data register Memory data register Data Register # Registers Register # Register # A B ALU ALUOut 5

51 Need for Additional Registers! register (IR) and memory data register (MDR): " Hold output of memory for an instruction read and a data read, respectively.! A and B registers: " Hold register operand values from register file.! ALUOut register: " Holds output of ALU. 5

52 Need for Additional Control Signals! All except the IR hold data only between a pair of adjacent clock cycles. Thus there is no need for a write control signal.! The IR needs to hold the instruction until the end of execution of that instruction. Thus it requires a write control signal.! Since several functional units are shared for different purposes, some multiplexors have to be added or expanded. Thus additional control signals are needed. 52

53 Simple Multicycle Datapath with Multiplexors Added new new PC M u x Address Write data Memory MemData [25 2] [2 6] [5 ] register [5 ] Memory data register M u [5 ] x M u x 6 register register 2 Registers Write register Write data Sign extend data data 2 32 Shift left 2 A B 4 M u x M u 2 x 3 Zero ALU ALU result ALUOut expanded 53

54 Complete Datapath and Control Unit for Multicycle Implementation PC M u x Address Write data Memory MemData [25 2] [2 6] [5 ] register [5 ] Memory data register PCWriteCond PCWrite IorD Outputs Mem MemWrite Control MemtoReg IRWrite Op [5 ] M u [5 ] x M u x PCSource ALUOp ALUSrcB ALUSrcA RegDst 6 RegWrite [25 ] Shift left 2 [3-26] PC [3-28] register register 2 Registers Write register Write data Sign extend data data 2 32 Shift left 2 A B 4 M u x M u 2 x 3 ALU control Zero ALU ALU result Jump address [3-] ALUOut 2 M u x [5 ] 54

55 Multiple Execution Steps Per! Typical execution steps: " fetch " decode and register fetch " Execution, memory address computation, or branch completion " Memory access or R-type instruction completion " Memory read completion! Each instruction takes a few (3-5) steps. 55

56 Summary of Execution Steps Step name Action for R- type instructions Action for memory reference instructions Action for branches Action for jumps fetch decode / register fetch IR = Memory[PC] PC = PC + 4 A = Reg[IR[25-2]] B = Reg[IR[2-6]] ALUOut = PC + (sign-extend(ir[5-]) << 2) Execution, address computation, branch/jump completion ALUOut = A op B ALUOut = A + sign-extend(ir[5-]) If (A == B) PC = ALUOut PC = PC[3-28] (IR[25-] << 2) Memory access or R- type completion Reg[IR[5-]] = ALUOut Load: MDR = Memory[ALUOut] or Store: Memory[ALUOut] = B Memory read completion Load: Reg[IR[2-6]] = MDR 56

57 Fetch Step! Fetch the instruction from memory and compute the address of the next sequential instruction: IR = Memory[PC]; PC = PC + 4;! Operations: " Send the PC to the memory as address. " an instruction from memory. " Write the instruction into the IR. " Increment the PC by 4. 57

58 Decode & Register Fetch Step! Assuming the existence of two registers and an offset field (no harm to do the computation early even if they do not exist), fetch the two registers from the register file and compute the branch target address: A = Reg[IR[25-2]]; B = Reg[IR[2-6]]; ALUOut = PC + (sign-extend(ir[5-]) << 2);! Operations: " Access the register file to read rs and rt. " Store the results into registers A and B. " Compute the branch target address (sign extension and left shift). " Store the address in ALUOut. 58

59 Execution, Memory Address Computation, or Branch Completion Step! In this step, the datapath operation is determined by the instruction class.! Memory reference instructions: " Compute the memory address: ALUOut = A + sign-extend(ir[5-]); " Operations: Sign-extend the 6-bit offset to a 32-bit value. Send both register A and the 32-bit offset to the ALU. Add the two values. Store the result in ALUOut. 59

60 Execution, Memory Address Computation, or Branch Completion Step! Arithmetic-logical (R-type) instructions: " Perform the ALU operation specified by the function code: ALUOut = A op B; " Operations: Send both registers A and B to the ALU. Perform the specified operation on the two values. Store the result in ALUOut. 6

61 Execution, Memory Address Computation, or Branch Completion Step! Branch instructions: " Compare registers A and B and set the PC to the branch target address if A and B are equal: if (A == B) PC = ALUOut; " Operations: Send both registers A and B to the ALU. Compare A and B by performing subtraction in the ALU and set the Zero output signal to if A and B are equal. If Zero is equal to, then write ALUOut to the PC. 6

62 Execution, Memory Address Computation, or Branch Completion Step! Jump instructions: " Compute the jump address and set the PC to this address: PC = PC[3-28] (IR[25-] << 2) " Operations: Left-shift the 26-bit address field by 2 bits to give a 28-bit value. Concatenate the four leftmost bits of the PC with the 28-bit value to form a 32-bit jump address. Write the jump address to the PC. 62

63 Memory Access or R-Type R Completion Step! Memory reference instructions: " from or write to memory: MDR = Memory[ALUOut]; // for load instruction or Memory[ALUOut] = B; // for store instruction " Operations: Use the address computed during the previous step and stored in ALUOut. For a load instruction, a data word is retrieved from memory with the specified address. For a store instruction, a data word is written into memory with the specified address. 63

64 Memory Access or R-Type R Completion Step! Arithmetic-logical (R-type) instructions: " Write the result of the ALU operation into a destination register inside the register file: Reg[IR[5-]] = ALUOut; " Operations: Get from ALUOut the value which was the result of the ALU operation in the previous step. Write the value into a register in the register file. 64

65 Memory Completion Step! A load instruction completes by writing back the value from memory into a register in the register file: Reg[IR[2-6]] = MDR;! Operations: " Get from MDR the value which was read from memory in the previous step. " Write the value into a register in the register file. 65

66 Control Unit Design! Unlike the single-cycle implementation which only requires a set of truth tables to specify the setting of the control signals based on the instruction class, control for the multicycle implementation is more complex because an instruction is executed in a series of steps and hence the signals for both the current step and the next step have to be specified.! Two techniques for specifying the control: " Finite state machine representation " Microprogramming 66

67 High-Level View of Finite State Machine Control for the Datapath Start fetch/decode and register fetch (Figure 5.37) Memory access instructions (Figure 5.38) R-type instructions (Figure 5.39) Branch instruction (Figure 5.4) Jump instruction (Figure 5.4) 67

68 Complete Finite State Machine Control 2 Memory address computation ALUSrcA = ALUSrcB = ALUOp = Start fetch Mem ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = 6 (Op = 'LW') or (Op = 'SW') Execution ALUSrcA = ALUSrcB = ALUOp= 8 (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSource = decode/ register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jump completion PCWrite PCSource = 3 (Op = 'LW') Memory access (Op = 'SW') 5 Memory access 7 R-type completion Mem IorD = MemWrite IorD = RegDst = RegWrite MemtoReg = 4 Write-back step RegDst= RegWrite MemtoReg= 68

69 Finite State Machine Controller Combinational control logic Datapath control outputs Outputs Inputs Next state Inputs from instruction register opcode field State register 69

70 Simplifying Control Design by Microprogramming! Representing the MIPS control using a finite state machine is relatively easy and feasible.! However, in case we have a large instruction set and a large number of complex addressing modes (e.g., Intel x86/pentium instruction set), the number of states in the finite state machine would go up to thousands, which becomes too large and cumbersome to handle.! The solution to this problem comes from programming - creating functions and procedures. " As programs become large, additional structuring techniques are needed to keep the programs comprehensible. 7

71 Microprogramming! Microinstructions: " The set of control signals that must be asserted in a state can be considered as an instruction to be executed by the datapath. " To distinguish such low-level control instructions from instructions of the MIPS instruction set, they are called microinstructions. " Executing a microinstruction has the effect of asserting the control signals specified by the microinstruction.! Microprogramming: designing the control unit as a program that implements machine instructions in terms of simpler microinstructions.! The asserted values on the control lines are represented symbolically in a microprogram, which is a representation of the microinstructions. 7

72 Microcode Controller Microcode storage Outputs Datapath control outputs Input Adder Microprogram counter Sequencing control Address select logic Inputs from instruction register opcode field 72

73 Key Concepts to Remember! Sequential logic circuits are needed for the implementation of state elements such as registers and memory units.! Latches and flip-flops are building blocks for state elements such as registers and some types of RAM.! A register file is a structure in the datapath consisting of a set of registers and some read and write ports.! There are two types of RAM: static RAM and dynamic RAM.! A two-stage decoding process is typically used in the addressing scheme of RAMs. 73

74 Key Concepts to Remember! A single-cycle implementation of the dathpath and control assumes that each instruction takes only one clock cycle.! Disadvantages of single-cycle implementation: long execution time and no sharing of hardware.! A multicycle implementation of the datapath and control allows different instructions to take different numbers of clock cycles.! Specification of the control for a multicycle implementation can be done using the finite state machine representation (for simple instruction sets) or through microprogramming (for complex instruction sets). 74