CMPE324 Computer Architecture Lecture 2
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1 CMPE324 Computer Architecture Lecture 2.1 What is Computer Architecture? Software Hardware Application (Netscape) Operating System Compiler (Unix; Assembler Windows 9x) Processor Memory Datapath & Control I/O system Instruction Set Architecture.2 Digital Design Circuit Design transistors, IC layout Key Idea: levels of abstraction CMPE324 hide unnecessary implementation details helps us cope with enormous complexity of real systems
2 What is Computer Architecture? Computer Architecture = Instruction Set Architecture (ISA).3 - boundary between hardware and software - the hardware s specification; defines what a machine does; + Machine Organization - how the hardware works; the implementation; must obey the ISA abstraction We will explore both Levels of Abstraction High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,mips) Assembler Machine Language Program (MIPS) temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $15, 0($2) lw $16, 4($2) sw sw $16, 0($2) $15, 4($2) Machine Interpretation Datapath Transfer Specification IR <- Imem[PC]; PC <- PC + 4.4
3 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Result Store Next Instruction Deposit results in storage for later use Determine successor instruction.5 MIPS Instructions Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with the MIPS instruction set architecture Design goals: maximize performance and minimize cost, reduce design time.6
4 Comparing Number of Instructions Code sequence for C = A + B for four classes of instruction sets: Stack Accumulator Register Register (register-memory) (load-store) Pop A Load A Load R1,A Load R1,A Pop B Add B Add R1,B Load R2,B Add Store C Store C, R1 Add R3,R1,R2 Push C Store C,R3 RISC machines (like MIPS) have only load-store instns. So, they are also called load-store machines. CISC machines may even have memory-memory instrns, like mem (A) = mem (B) + mem (C ).7 General Purpose Registers Dominate Advantages of registers: 1. registers are faster than memory 2. registers are easier for a compiler to use 3. registers can hold variables memory traffic is reduced, so program is sped up (since registers are faster than memory) code density improves (since register named with fewer bits than memory location) MIPS Registers: 31 x 32-bit GPRs, (R0 =0), 32 x 32-bit FP regs (paired DP).8
5 Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data.9 Addressing: Byte vs. word Every word in memory has an address, similar to an index in an array Early computers numbered words like C numbers elements of an array: Memory[0], Memory[1], Memory[2], Today machines address memory as bytes, hence word addresses differ by 4 Memory[0], Memory[4], Memory[8], Called the address of a word Computers needed to access 8-bit bytes as well as words (4 bytes/word) Called byte addressing.10
6 Little/Big Endian convention Big Endian: address of most significant byte = word address For example, MIPS Little Endian: address of least significant byte = word address For example, Intel 80x86 msb big endian little endian lsb.11 Addressing Modes Addressing mode Example Meaning Register Add R4,R3 R4 R4+R3 Immediate Add R4,#3 R4 R4+3 Displacement Add R4,100(R1) R4 R4+Mem[100+R1] Register indirect Add R4,(R1) R4 R4+Mem[R1] Indexed / Base Add R3,(R1+R2) R3 R3+Mem[R1+R2] Direct or absolute Add R1,(1001) R1 R1+Mem[1001].12
7 Typical Operations (little change since 1960 Data Movement Load (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmetic Shift Logical Control (Jump/Branch) Subroutine Linkage integer (binary + decimal) or FP Add, Subtract, Multiply, Divide shift left/right, rotate left/right not, and, or, set, clear unconditional, conditional call, return...13 Instruction Format Field Names Fields have names: (R-type Inst.) op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op: basic operation of instruction, opcode rs: 1st register source operand rt: 2nd register source operand rd: register destination operand, gets the result shamt: shift amount (use later, so 0 for now) funct: function; selects the specific variant of the operation in the op field; sometimes called the function code.14
8 Notes about Register and Imm. Formats 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R: op rs rt rd shamt funct I: op rs rt address 6 bits 5 bits 5 bits 16 bits To make it easier for hardware (HW), 1st 3 fields same in R-format and I-format rt field meaning changed.15 R-format: rt is 2nd source operand I-format: rt can be destination operand How does HW know which format is which? Distinct values in 1st field (op) tell whether last 16 bits are 3 fields (R-format) or 1 field (I-format) Notes about Register and Imm. Formats How does HW know which format is which? Distinct values in 1st field (op) tell whether last 16 bits are 3 fields (R-format) or 1 field (I-format) Inst. type R op= 0 rs rt rd shamt func I op= 1, 4-62 rs rt Immediate J op= 2, 3 target address.16
9 MIPS Instruction Encoding Examples of some Opcodes: Instruction Format Opcode shamt funct Add R Sub R Shift (by 4) R Add (imm) I 8 n.a n.a Lw (load word) I 35 n.a n.a Sw (store word) I 43 n.a n.a.17 Tanslating to MIPS Machine Language From the instruction set, Opcode for Lw is 35. Opcode for add is 0 with funct 32. From register assignment table, t0=8, s1=17, s2=18 and s3=19. Instruction consists of op=6 bits, rs=5bits, rt=5bits, rd=5bits, shamt=5bits and funct=6bits for R format and address=16 bits instead of rd,shamt and funct for I format: total=32 bits Assembly language lw $t0, 1200($s3) add $s1,$s2,$t0 translate to: op rs rt rd address/shamt funct
10 MIPS Addressing Modes/Instruction Format All instructions 32 bits wide Register (direct) op rs rt rd register Immediate op rs rt immed Base+index op rs rt immed Memory register + PC-relative op rs rt immed Memory PC +.19 MIPS Instruction Formats simple instructions all 32 bits wide only three instruction formats R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address.20
11 MIPS Instructions: Name Example Comments $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero alw ays equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so 2 30 memory Memory[4],..., sequential w ords differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers, such as those saved on procedure calls. MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants load word lw $s1, 100($s2) $s1 = Memory[$s ] Word from memory to register store word sw $s1, 100($s2) Memory[$s ] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s ] Byte from memory to register store byte sb $s1, 100($s2) Memory[$s ] = $s1 Byte from register to memory load upper immediate lui $s1, $s1 = 100 * 2 Loads constant in upper 16 bits branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC Equal test; PC-relative branch.21 branch on not equal bne $s1, $s2, 25 if ($s1!= $s2) go to Conditional PC branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0 set less than immediate slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0 Not equal test; PC-relative Compare less than; for beq, bne Compare less than constant jump j 2500 go to Jump to target address Uncondi- jump register jr $ra go to $ra For switch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to For procedure call Assembly Operands: Registers Naming of 32 MIPS registers: instead of r0, r1,, r31, use $s0, $s1, for registers corresponding to C variables $t0, $t1, for registers corresponding to temporary variables Will explain mapping convention later of $s0, $s1,, $t0, $t1,, to r0, r1, Note: whereas C declares its variables (e.g., int fahr), Assembly operands (registers) are fixed and not declared.22
12 Policy of Use Conventions Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address.23 Role of Registers vs. Memory What if more variables than registers? Compiler tries to keep most frequently used variables in registers Writing less common to memory: spilling Why not keep all variables in memory? Smaller is faster: registers are faster than memory Registers more versatile: - MIPS arithmetic instruction can read 2, operate on them, and write 1 per instruction - MIPS data transfer only read or write 1 operand per instruction, and no operation.24
13 Compilation using Registers Compile by hand using registers: f = (g + h) - (i + j); Register Allocations: f: $s0, g: $s1, h: $s2, i: $s3, j: $s4 MIPS Instructions: add $s0,$s1,$s2 add $t1,$s3,$s4 sub $s0,$s0,$t1 # $s0 = g+h # $t1 = i+j # f=(g+h)-(i+j).25 Data Transfer Instruction: Memory to Reg Load: moves data from memory to register Syntax: 1) operation name 2) register to be loaded 3) constant and register to access memory MIPS name, lw for load word: Example: lw $t0, 8($s3).26 Called offset Called base register or base address register or base address
14 Compilation when Operand is in Memory Q: Compile by hand using registers: g = h + A[300]; g:$s1, h:$s2, $s3:starting (base) address of array A Since A[300] is in memory, 1st transfer from memory to (temporary) register: lw $t0,300($s3) # Adds 300 to $s3 to select A[300], puts into $t0 lw $t0,1200($s3) # For byte addressable machines 300x4 Next add it to h and place in g add $s1,$s2,$t0 # $s1= h+a[300] HW: Compile A[300] = h + A[300].27 Compile with variable index What if array index not a constant? g = h + A[i]; g:$s1, h:$s2, i:$s4, $s3:base address of A To load A[i] into a register, first turn i into a byte address; multiply by 4 How multiply using adds? i + i = 2i, 2i + 2i = 4i add $t1,$s4,$s4 # $t1 = 2*i add $t1,$t1,$t1 # $t1 = 4*i.28
15 Compile with variable index, con t Next add to base of A: add $t1,$t1,$s3 #$t1=address of #A[i] (4*i+$s3) Now load A[i] into a temporary register: lw $t0,0($t1) # Temp $t0 = A[i] Finally add to h and put sum in g: add $s1,$s2,$t0 # g = h + A[i].29 MIPS arithmetic instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; subtract sub $1,$2,$3 $1 = $2 $3 3 operands; add immediate addi $1,$2,100 $1 = $ constant; add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; subtract unsigned subu $1,$2,$3 $1 = $2 $3 3 operands; add imm. unsign. addiu $1,$2,100 $1 = $ constant; multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo.30
16 MIPS logical instructions Instruction Example Meaning Comment and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND or or $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical OR xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR nor nor $1,$2,$3 $1 = ~($2 $3) 3 reg. operands; Logical NOR and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant or immediate ori $1,$2,10 $1 = $2 10 Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable.31 MIPS decision instructions Decision instruction in MIPS: beq register1, register2, L1 beq is Branch if (registers are) equal Same meaning as (using C): if (register1==register2) go to L1 Complementary MIPS decision instruction bne register1, register2, L1 bne is Branch if (registers are) not equal Same meaning as (using C): if (register1!=register2) go to L1 unconditional jump instruction j J Next instruction.32
17 C M I P S Compiling C if into MIPS: Summary Compile by hand if (i == j) f=g+h; else f=g-h; Mapping f: $s0, g: $s1, h: $s2, i: $s3, j: $s4 (true) i == j f=g+h i == j? f=g-h (false) i!= j beq $s3,s4, True # branch i==j sub $s0,$s1,$s2 # f=g-h(false) j Exit # go to Exit True: add $s0,$s1,$s2 # f=g+h (true) Exit:.33 Loops in C/Assembly: Summary C M I P S Loop: g = g + A[i]; i = i + j; if (i!= h) goto Loop; (g,h,i,j:$s1,$s2,$s3,$s4 : base of A[]:$s5) Loop: add $t1,$s3,$s3 #$t1= 2*i add $t1,$t1,$t1 #$t1= 4*i add $t1,$t1,$s5 #$t1=addr A lw $t1,0($t1) #$t1=a[i] add $s1,$s1,$t1 #g=g+a[i] add $s3,$s3,$s4 #i=i + j bne $s3,$s2,loop# goto Loop # if i!=h.34
18 I Branch Addressing: PC-relative Conditional Branch: beq $t0,$t1,label op rs rt address 6 bits 5 bits 5 bits 16 bits address just 16 bits (2 16 ), program too small! Option: always add address to a register PC = Register + Branch address Change register contents => bigger programs Which register? How use conditional branch? if-else, loops Near current instruction => use PC as reg! PC-relative addressing (PC+4) +/ words.35 J J Branch Addressing: Jumps, J format j label # go to label j has only one operand; add format op address 6 bits 26 bits large address allows large programs bright idea: address of instruction always multiple of 4 (instructions always words) => store number of word, save 2 bits Example: j exit # exit = PC = address * 4 + upper 4 bits of old PC.36
19 .37 Branch Addressing: PC-relative Example Loop: slt $t1,$zero,$a1 # t1=9,a1=5 beq $t1,$zero,exit # no=>exit add $t0,$t0,$a0 # t0=8,a0=4 subi $a1,$a1,1 # a1=5 j Loop # goto Loop Exit: add $v0,$t0,$zero # v0=2,t0=8 Set t1=1 if $zero < $a1 Address = *4 While in C/Assembly: Summary C.38 while (save[i]==k) i = i + j; (i,j,k: $s3,$s4,$s5: base of save[]:$s6) Loop: add $t1,$s3,$s3 #$t1 = 2*i add $t1,$t1,$t1 #$t1 = 4*i M add $t1,$t1,$s6 #$t1=addr I lw $t1,0($t1) #$t1=save[i] bne $t1,$s5,exit#goto Exit P #if save[i]!=k S add $s3,$s3,$s4 # i = i + j j Loop # goto Loop Exit:
20 If less in C/Assembly C M I P S if (g < h) go to Less slt $t0,$s0,$s1 # $t0 = 1 if # $s0<$s1 (g<h) bne $t0,$zero, Less # goto Less # if $t0!=0... # (if (g<h)) Less: A branch if $t0!= 0 branches if g < h. Register $zero always 0, so use bne comparing register $t0 to register $zero.39 How test if (g >= h)? C case/switch statement Choose among four alternatives depending on whether k has the value 0, 1, 2, or 3 switch (k) { } case 0: f=i+j; break; /* k=0*/ case 1: f=g+h; break; /* k=1*/ case 2: f=g h; break; /* k=2*/ case 3: f=i j; break; /* k=3*/.40
21 Case/Switch via Jump Address Table Notice that last case must wait for n-1 tests before executing, making it slow Alternative tries to go to all cases equally fast: jump address table for scale-ability Idea: encode alternatives as a table of addresses of the cases - Table is an array of words with addresses corresponding to case labels Program indexes into table and jumps MIPS instruction jump register (jr) unconditionally branches to address in register; use load to get address.41 Jump Address Table: Summary slti $t3,$s5,0 #Test if k < 0 bne $t3,$zero,exit #if k<0,goto Exit slti $t3,$s5,4 # Test if k < 4 beq $t3,$zero,exit #if k>=4,goto Exit add $t1,$s5,$s5 # Temp reg $t1 = 2*k add $t1,$t1,$t1 # Temp reg $t1 = 4*k add $t1,$t1,$t2 #$t1=addr JumpTable[k] lw $t1,0($t1) # $t1 = JumpTable[k] jr $t1 # jump based on $t1 L0: add $s0,$s3,$s4 # k=0 so f = i + j j Exit # end case, goto Exit L1: add $s0,$s1,$s2 # k=1 so f = g + h j Exit # end case, goto Exit L2: sub $s0,$s1,$s2 # k=2 so f = g h j Exit # end case, goto Exit L3: sub $s0,$s3,$s4 # k=3 so f = i j Exit: # end of switch statement.42
22 MIPS Instruction Set Revealed So Far MIPS Instructions: arithmetic: add, sub, addi, slt, slti data transfer: lw, sw conditional branch: beq, bne unconditional branch: j, jr Machine Language Formats: R-Register I-Immediate J- Jump.43 Pseudo-instructions MIPS assemblers support pseudo-instructions that give the illusion of a more expressive instruction set, but are actually translated into one or more simpler, real instructions. li and move pseudo-instructions: li $a0, 2000 # Load immediate 2000 into $a0 move $a1, $t0 # Copy $t0 into $a1 They are probably clearer than their corresponding MIPS instructions: addi $a0, $0, 2000 # Initialize $a0 to 2000 add $a1, $t0, $0 # Copy $t0 into $a1 We ll see lots more pseudo-instructions this semester. Unless otherwise stated, you can always use pseudo-instructions in your assignments and on exams. 44
23 Pseudo-branches The MIPS processor only supports two branch instructions, beq and bne, but to simplify your life the assembler provides the following other branches: blt $t0, $t1, L1 // Branch if $t0 < $t1 ble $t0, $t1, L2 // Branch if $t0 <= $t1 bgt $t0, $t1, L3 // Branch if $t0 > $t1 bge $t0, $t1, L4 // Branch if $t0 >= $t1 There are also immediate versions of these branches, where the second source is a constant instead of a register. 45 Implementing pseudo-branches Most pseudo-branches are implemented using slt. For example, a branchif-less-than instruction blt $a0, $a1, Label is translated into the following. slt $at, $a0, $a1 // $at = 1 if $a0 < $a1 bne $at, $0, Label // Branch if $at!= 0 This supports immediate branches, which are also pseudo-instructions. For example, blti $a0, 5, Label is translated into two instructions. slti $at, $a0, 5 // $at = 1if $a0 < 5 bne $at, $0, Label // Branch if $a0 < 5 All of the pseudo-branches need a register to save the result of slt, even though it s not needed afterwards. MIPS assemblers use register $1, or $at, for temporary storage. You should be careful in using $at in your own programs, as it may be overwritten by assembler-generated code. 46
24 Translating an if-then statement (revisited) We can use branch instructions to translate if-then statements into MIPS assembly code. v0 = *a0; lw $v0, 0($a0) if (v0 < 0) bgt $v0, 0, skip v0 = -v0; sub $v0, $zero, $v0 v1 = v0 + v0; skip: add $v1, $v0, $v0 Sometimes it s easier to invert the original condition. In this case, we changed continue if v0 < 0 to skip if v0 >= 0. This saves a few instructions in the resulting assembly code. 47 Translating an if-then-else statements (revisited) If there is an else clause, it is the target of the conditional branch And the then clause needs a jump over the else clause // increase the magnitude of v0 by one if (v0 < 0) bge $v0, $0, E v0 --; sub $v0, $v0, 1 j L else v0 ++; E: add $v0, $v0, 1 v1 = v0; L: move $v1, $v0 Dealing with else-if code is similar, but the target of the first branch will be another if statement. Drawing the control-flow graph can help you out. 48
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