# Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

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1 Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook)

2 Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2

3 Introduction Chapter 2.1 Chapter 2 Instructions: Language of the Computer 3

4 Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers had very simple instruction sets Simplified implementation Many modern computers also have simple instruction sets 2.1 Introduction Chapter 2 Instructions: Language of the Computer 4

5 The MIPS Instruction Set Used as the example throughout the book 32-bit Computer, i.e., MIPS-32 Stanford MIPS commercialized by MIPS Technologies ( Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs See MIPS Reference Data tear-out card, and Appendixes A and E Chapter 2 Instructions: Language of the Computer 5

6 Represent numbers in computer Chapter 2.4 Chapter 2 Instructions: Language of the Computer 6

7 How to represent integers in a computer? Unsigned integer Signed integer Two s complement Sign extension Chapter 2 Instructions: Language of the Computer 7

8 Unsigned Binary Integers Given an n-bit number x x n 1 n n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers = = = Using 32 bits 0 to +4,294,967,295 Chapter 2 Instructions: Language of the Computer 8

9 2s-Complement Signed Integers Given an n-bit number x x n 1 n n 12 xn 22 x12 x02 Range: 2 n 1 to +2 n 1 1 Example = = 2,147,483, ,147,483,644 = 4 10 Using 32 bits 2,147,483,648 to +2,147,483,647 Chapter 2 Instructions: Language of the Computer 9

10 2s-Complement Signed Integers Bit 31 is sign bit 1 for negative numbers 0 for non-negative numbers 2 n 1 can t be represented Non-negative numbers have the same unsigned and 2s-complement representation Some specific numbers 0: : Most-negative: Most-positive: Chapter 2 Instructions: Language of the Computer 10

11 Signed Negation Complement and add 1 Complement means 1 0, 0 1 x x x 1 x Example: negate = = = Chapter 2 Instructions: Language of the Computer 11

12 Sign Extension Representing a number using more bits Preserve the numeric value In MIPS instruction set addi: extend immediate value lb, lh: extend loaded byte/halfword beq, bne: extend the displacement Replicate the sign bit to the left c.f. zero extension: extend with 0s Examples: 8-bit to 16-bit +2: => : => Chapter 2 Instructions: Language of the Computer 12

13 Overflow The result of an arithmetic operation is beyond the representation How to decide if overflow occurs Unsigned operations Signed operations Chapter 2 Instructions: Language of the Computer 13

14 Representation of Memory Addresses Memory addresses are given in the unit of byte A multiple-byte word is stored in multiple consecutive bytes The address of a word matches the address of one of the multiple bytes within the word Use the smallest address in general In MIPS, words must start at addresses of multiples of 4 Chapter 2 Instructions: Language of the Computer 14

15 Store words into memory Chapter 2 Instructions: Language of the Computer 15

16 Two Key Principles of Machine Design 1. Instructions are represented as numbers and, as such, are indistinguishable from data 2. Programs are stored in alterable memory (that can be read or written to) just like data Stored-program concept Programs can be shipped as files of binary numbers Computers can inherit ready-made software provided they are compatible with an existing ISA leads industry to align around a small number of ISAs Chapter 2 Instructions: Language of the Computer 16

17 Representing Instructions in the Computer Chapter 2.5 Chapter 2 Instructions: Language of the Computer 17

18 MIPS-32 ISA Instruction Categories Computational Load/Store Jump and Branch Floating Point Memory Management Special 3 Instruction Formats: all 32 bits wide op op op rs rt rd sa funct rs rt immediate jump target R format I format J format Chapter 2 Instructions: Language of the Computer 18

19 32 Registers Name Register Number Usage Preserved by callee? \$zero 0 constant 0 (hardware) n.a. \$at 1 reserved for assembler n.a. \$v0 - \$v1 2-3 returned values no \$a0 - \$a3 4-7 arguments no \$t0 - \$t temporaries no \$s0 - \$s saved values yes \$t8 - \$t temporaries no \$gp 28 global pointer yes \$sp 29 stack pointer yes \$fp 30 frame pointer yes \$ra 31 return address no Chapter 2 Instructions: Language of the Computer 19

20 MIPS Register File Holds thirty-two 32-bit registers Two read ports One write port Registers are Faster than main memory Register files with more locations are slower Easier for a compiler to use src1 addr src2 addr dst addr write data (A*B)+(C*D)-(E*F) can do multiplications in any order Register File 32 bits 32 locations write control src1 data src2 data Chapter 2 Instructions: Language of the Computer 20

21 Registers vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores Compiler must use registers for variables as much as possible Only spill the less frequently used variables to memory Register optimization is important! Chapter 2 Instructions: Language of the Computer 21

22 MIPS (RISC) Design Principles Simplicity favors regularity Fixed size instructions Small number of instruction formats Opcode is always the 6 most significant bits Smaller is faster Limited instruction set Limited number of registers Limited number of addressing mode Make the common case fast Arithmetic operands from the register file (load-store machine) Allow instructions to contain immediate operands Good design demands good compromises Three instruction formats Chapter 2 Instructions: Language of the Computer 22

23 MIPS R-format Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction fields op: operation code (opcode) All R-type instructions use opcode rs: register file address of the first source operand rt: register file address of the second source operand rd: register file address of the result s destination shamt: shift amount (for shift instructions) funct: function code augmenting the opcode Chapter 2 Instructions: Language of the Computer 23

24 R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add \$t0, \$s1, \$s2 special \$s1 \$s2 \$t0 0 add ,0010,0011,0010,0100,0000,0010, = Chapter 2 Instructions: Language of the Computer 24

25 R-type Arithmetic Instructions Chapter 2 Instructions: Language of the Computer 25

26 R-type Arithmetic Instructions Chapter 2 Instructions: Language of the Computer 26

27 Register Operand Example C code: f = (g + h) - (i + j); f, g, h, i, j in \$s0, \$s1, \$s2, \$s3, \$s4 Compiled MIPS code: add \$t0, \$s1, \$s2 # \$t0 = g + h add \$t1, \$s3, \$s4 # \$t1 = i + j sub \$s0, \$t0, \$t1 # f = \$t0 - \$t1 Chapter 2 Instructions: Language of the Computer 27

28 MIPS I-format Instructions op rs rt immediate or address 6 bits 5 bits 5 bits 16 bits Immediate arithmetic and load/store instructions Immediate arithmetic addi \$rt, \$rs, Imm #R[rt]=R[rs]+SignExtImm rt: destination register number rs: source register number immediate: 2 15 to , sign extension to 32 bits Chapter 2 Instructions: Language of the Computer 28

29 Immediate Operands Constant data specified in an instruction addi \$s3, \$s3, 4 No subtract immediate instruction Just use a negative constant addi \$s2, \$s1, opcode rs rt immediate FFFF 16 Chapter 2 Instructions: Language of the Computer 29

30 The Constant Zero MIPS register 0 (\$zero) is the constant 0 Cannot be overwritten Useful for common operations E.g., move between registers add \$t2, \$s1, \$zero Chapter 2 Instructions: Language of the Computer 30

31 Unsigned Arithmetic Instructions addu: Add Unsigned addu \$rd, \$rs, \$rt # R[rd]=R[rs]+R[rt] addiu: Add Immediate Unsigned addiu \$rt, \$rs, Imm # R[rt]=R[rs]+SignExtImm subu: Subtract Unsigned subu \$rd, \$rs, \$rt # R[rd]=R[rs]-R[rt] Chapter 2 Instructions: Language of the Computer 31

32 Memory Operations Chapter 2 Instructions: Language of the Computer 32

33 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at the least address of a word c.f. Little Endian: least-significant byte at the least address Chapter 2 Instructions: Language of the Computer 33

34 MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw \$t0, 4(\$s3) # load a word from memory sw \$t0, 8(\$s3) # store a word to memory The data are loaded into (lw) or stored from (sw) a register in the register file The memory address, a 32-bit address, is formed by adding the offset value to the content of the base address register A 16-bit field means accessing is limited to memory locations within a region of ±2 13 or ± 8,192 words (± 2 15 or ± 32,768 bytes) of the address in the base register Chapter 2 Instructions: Language of the Computer 34

35 MIPS I-format Instructions op rs rt Address (offset) 6 bits 5 bits 5 bits 16 bits load/store instructions lw/sw \$rt, offset(\$rs) rt: destination (for load) or source (for store) register number Address: offset added to base address in rs Offset range: 2 15 to Chapter 2 Instructions: Language of the Computer 35

36 Machine Language Load Instruction Load/Store Instruction Format (I format) Chapter 2 Instructions: Language of the Computer 36

37 Memory Operand Example 1 C code: g = h + A[8]; g in \$s1, h in \$s2, base address of A in \$s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw \$t0, 32(\$s3) # load word add \$s1, \$s2, \$t0 offset base register Chapter 2 Instructions: Language of the Computer 37

38 Memory Operand Example 2 C code: A[12] = h + A[8]; h in \$s2, base address of A in \$s3 Compiled MIPS code: Index 8 requires offset of 32 lw \$t0, 32(\$s3) # load word add \$t0, \$s2, \$t0 sw \$t0, 48(\$s3) # store word Chapter 2 Instructions: Language of the Computer 38

39 Loading and Storing Bytes MIPS provides special instructions to move bytes lb \$t0, 1(\$s3) # load byte from memory lbu \$t0, 1(\$s3) # load unsigned byte from memory sb \$t0, 6(\$s3) # store byte to memory 0x bit offset What 8 bits get loaded and stored? Load byte places the byte from memory in the rightmost 8 bits of the destination register lb: the byte is sign-extended to 32 bits lbu: the byte is zero-extended to 32 bits Store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory Leave the other bits in the memory word intact Chapter 2 Instructions: Language of the Computer 39

40 Loading and Storing Half Words MIPS provides special instructions to move half words, i.e., 16 bits lh \$t0, 2(\$s3) # load half word from memory lhu \$t0, 4(\$s3) # load unsigned half word from memory sh \$t0, 8(\$s3) # store half word to memory 0x bit offset The address of the harf word has to be even Byte_3 Byte_2 Byte_1 Byte_0 Chapter 2 Instructions: Language of the Computer 40

41 Logical Operations Chapter 2.6 Chapter 2 Instructions: Language of the Computer 41

42 Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT ~ ~ nor 2.6 Logical Operations Useful for extracting and inserting groups of bits in a word Chapter 2 Instructions: Language of the Computer 42

43 Shift Operations - sll op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits shamt: how many positions to shift Shift left logical Shift left and fill with 0 bits sll by i bits: multiplies by 2 i sll \$rd, \$rt, shamt # R[rd]=R[rt]<<shamt sll \$t0, \$t0, bits 5 bits 5 bits 5 bits 5 bits 6 bits Chapter 2 Instructions: Language of the Computer 43

44 Shift Operations - srl op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits shamt: how many positions to shift Shift right logical Shift right and fill with 0 bits srl by i bits: divides by 2 i For non-negative number only srl \$rd, \$rt, shamt # R[rd]=R[rt]>>shamt srl \$s0, \$t0, bits 5 bits 5 bits 5 bits 5 bits 6 bits Chapter 2 Instructions: Language of the Computer 44

45 Bitwise Operations Bitwise logical operations in MIPS ISA and \$rd, \$rs, \$rt # R[rd] = R[rs] & R[rt] or \$rd, \$rs, \$rt # R[rd] = R[rs] R[rt] nor \$rd, \$rs, \$rt # R[rd] = ~ (R[rs] R[rt]) Instruction Format (R format) op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits nor \$t0, \$t1, \$t x24 Chapter 2 Instructions: Language of the Computer 45

46 AND Operations Useful to mask bits in a word Select some bits, clear others to 0 and \$t0, \$t1, \$t2 \$t2 \$t1 \$t Chapter 2 Instructions: Language of the Computer 46

47 OR Operations Useful to include bits in a word Set some bits to 1, leave others unchanged or \$t0, \$t1, \$t2 \$t2 \$t1 \$t Chapter 2 Instructions: Language of the Computer 47

48 NOT Operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS does not have NOT instruction MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b ) nor \$t0, \$t1, \$zero Register 0: always read as zero \$t1 \$t Chapter 2 Instructions: Language of the Computer 48

49 Logical Operations with Immediate Bitwise logical operations with immediate andi \$rt, \$rs, Imm # R[rt] = R[rs] & ZeroExtImm ori \$rt, \$rs, Imm # R[rt] = R[rs] ZeroExtImm Instruction Format (I format) op rs rt Immediate 6 bits 5 bits 5 bits 16 bits andi \$t0, \$t1, 0xFF00 0x0C 9 8 0xFF00 6 bits 5 bits 5 bits 16 bits Chapter 2 Instructions: Language of the Computer 49

50 Branch and Jump Instructions Chapter 2.7 Chapter 2 Instructions: Language of the Computer 50

51 Control Flow Instructions Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq \$rs, \$rt, L1 if (rs == rt) branch to instruction labeled L1; bne \$rs, \$rt, L1 if (rs!= rt) branch to instruction labeled L1; Instruction Format (I format) 2.7 Instructions for Making Decisions op rs rt Offset 6 bits 5 bits 5 bits 16 bits Chapter 2 Instructions: Language of the Computer 51

52 Compiling If Statements C code: if (i==j) f = g+h; else f = g-h; f,g,h,i,j in \$s0,\$s1,\$s2,\$s3,\$s4 Compiled MIPS code: bne \$s3, \$s4, Else add \$s0, \$s1, \$s2 j Exit Else: sub \$s0, \$s1, \$s2 Exit: Assembler calculates addresses Chapter 2 Instructions: Language of the Computer 52

53 Compiling If Statements C code: if (i==j) f = g+h; else f = g-h; f,g,h,i,j in \$s0,\$s1,\$s2,\$s3,\$s4 Compiled MIPS code: beq \$s3, \$s4, If sub \$s0, \$s1, \$s2 j Exit If: add \$s0, \$s1, \$s2 Exit: Assembler calculates addresses Chapter 2 Instructions: Language of the Computer 53

54 Control Flow Instructions Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq \$rs, \$rt, L1 bne \$rs, \$rt, L1 Instruction Format (I format) 2.7 Instructions for Making Decisions op rs rt Offset 6 bits 5 bits 5 bits 16 bits How to specify the branch destination address? Chapter 2 Instructions: Language of the Computer 54

55 Specifying Branch Destinations Use a base address (like in lw) added to the 16-bit offset Which register? Instruction Address Register (Program Counter) Its use is automatically implied by instructions PC gets updated (PC+4) during the fetch stage so that it holds the address of the next instruction Instruction address is always the multiple of 4. The unit of the offset is word Limit the branch distance to to (word) instructions from the instruction after the branch instruction Chapter 2 Instructions: Language of the Computer 55

56 Compiling Loop Statements C code: while (save[i] == k) i += 1; i in \$s3, k in \$s5, address of save in \$s6 Compiled MIPS code: Loop: sll \$t1, \$s3, 2 add \$t1, \$t1, \$s6 lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit addi \$s3, \$s3, 1 j Loop Exit: Chapter 2 Instructions: Language of the Computer 56

57 Branch Instruction Design Why not blt, bge, etc? Hardware for <,, slower than =, Combining with branch involves more work per instruction, requiring a slower clock All instructions are penalized! beq and bne are the common case This is a good design compromise Chapter 2 Instructions: Language of the Computer 57

58 In Support of Branch Instructions We have beq, bne, but what about other kinds of branches (e.g., branch-if-less-than)? Set on less than instruction: slt \$rd, \$rs, \$rt if (rs < rt) rd = 1; else rd = 0; Instruction format: R format Alternate versions of slt sltu \$rd, \$rs, \$rt slti \$rt, \$rs, Imm sltiu \$rt, \$rs, Imm Chapter 2 Instructions: Language of the Computer 58

59 Signed vs. Unsigned Signed comparison: slt, slti Unsigned comparison: sltu, sltui Example \$s0 = \$s1 = slt \$t0, \$s0, \$s1 # signed 1 < +1 \$t0 = 1 sltu \$t0, \$s0, \$s1 # unsigned +4,294,967,295 > +1 \$t0 = 0 Chapter 2 Instructions: Language of the Computer 59

60 Pseudo Branch Instructions Can use slt, beq, bne, and the register \$zero to create other conditions less than blt \$s1, \$s2, Label slt \$at, \$s1, \$s2 #\$at set to 1 if bne \$at, \$zero, Label #\$s1 < \$s2 less than or equal to ble \$s1, \$s2, Label greater than bgt \$s1, \$s2, Label greater than or equal to bge \$s1, \$s2, Label Such branches are included in the instruction set as pseudo instructions - recognized and expanded by the assembler Assembler needs a reserved register (\$at) Chapter 2 Instructions: Language of the Computer 60

61 Unconditional Jump Jump (j) targets could be anywhere in text segment within 256 MB Encode full address in instruction Instruction format: J format op address 6 bits 26 bits (Pseudo)Direct jump addressing Target address = (PC+4) :(address 4) PC is the address of the jump instruction Chapter 2 Instructions: Language of the Computer 61

62 Form the target address from the low order 26 bits of the jump instruction PC Where the 4 bits come from? The upper 4 bits of the address of the instruction following the Jump instruction Chapter 2 Instructions: Language of the Computer 62

63 Target Addressing Example Loop code from earlier example Assume Loop at location Loop: sll \$t1, \$s3, add \$t1, \$t1, \$s lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit addi \$s3, \$s3, j Loop Exit: Chapter 2 Instructions: Language of the Computer 63

64 Target Addressing Example Loop code from earlier example Assume Loop at location Loop: sll \$t1, \$s3, add \$t1, \$t1, \$s lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit addi \$s3, \$s3, j Loop Exit: Chapter 2 Instructions: Language of the Computer 64

65 Branching Far Away If branch target is too far to encode with 16-bit offset, assembler rewrites the code Example beq \$s0,\$s1, L1 bne \$s0,\$s1, L2 j L1 L2: Chapter 2 Instructions: Language of the Computer 65

66 Procedure Call Convention and Support Chapter 2.8 Chapter 2 Instructions: Language of the Computer 66

67 Six Steps in Execution of a Procedure 1. Main routine (caller) places parameters in a place where the procedure (callee) can access them \$a0-\$a3: four argument registers 2. Caller transfers control to the callee 3. Callee acquires the storage resources needed 4. Callee performs the desired task 5. Callee places the result value in a place where the caller can access it \$v0-\$v1: two registers for result values 6. Callee returns control to the caller \$ra: return address register to return to the point of origin Chapter 2 Instructions: Language of the Computer 67

68 Instructions for Accessing Procedures MIPS procedure call instruction Saves PC+8 in register \$ra to have a link to the second instruction following the jump instruction for the procedure to return jal ProcedureAddress #jump and link Instruction format: J format 0x03 26 bit address Procedure can do a jump on register jr \$ra #return Instruction format: R format 0 rs 0x08 Chapter 2 Instructions: Language of the Computer 68

69 Calling Convention A set of rules for defining Where data are placed during function calls Who saves/restores data What data should be stored All calling conventions have a bit in common All store data in registers and on a stack Chapter 2 Instructions: Language of the Computer 69

70 32 Registers Revisited Name Register Number Usage Preserved by callee? \$zero 0 constant 0 (hardware) n.a. \$at 1 reserved for assembler n.a. \$v0 - \$v1 2-3 returned values no \$a0 - \$a3 4-7 arguments no \$t0 - \$t temporaries no \$s0 - \$s saved values yes \$t8 - \$t temporaries no \$gp 28 global pointer yes \$sp 29 stack pointer yes \$fp 30 frame pointer yes \$ra 31 return address no Chapter 2 Instructions: Language of the Computer 70

71 MIPS Memory Allocation Text: program code Static data: global variables e.g., static variables in C, constant arrays and strings \$gp initialized to address allowing ±offsets into this segment Dynamic data: heap E.g., malloc in C, new in Java Stack: automatic storage \$sp \$gp PC Memory Stack Dynamic data (heap) Static data Text (Your code) Reserved 0x 7f f f f f f c 0x x x x Chapter 2 Instructions: Language of the Computer 71

72 Local Data on the Stack Local data allocated by callee e.g., C automatic variables Procedure frame (activation record) Used by some compilers to manage stack storage Chapter 2 Instructions: Language of the Computer 72

73 Stack A stack is a LIFO data structure LIFO = Last-In, First-Out Basic stack operations: push, pop Stack pointer: point to the top element in the stack Push: Place an element on the top of the stack Update the stack pointer Pop: Remove an element from the top of the stack Update the stack pointer Chapter 2 Instructions: Language of the Computer 73

74 Stack Example sp -6 sp sp 15 sp : initial state 2: push(15) 3: push(-6) 4: pop sp 16 sp -3 sp sp : push(10) 6: push(16) 7: pop 8: push(-3) Chapter 2 Instructions: Language of the Computer 74

75 Stack in Memory A stack is a last-in first-out (LIFO) data structure high addr low addr top of stack \$sp One of the general registers, \$sp, is used to address the stack, which grows from high address to low address Push add data onto the stack \$sp = \$sp 4 data on stack at new \$sp Pop remove data from the stack data from stack at \$sp \$sp = \$sp + 4 Chapter 2 Instructions: Language of the Computer 75

76 Procedures Root Entry function of a program Always a caller Non-leaf procedure Both a caller and a callee Leaf procedure Always a callee Chapter 2 Instructions: Language of the Computer 76

77 Calling Conventions regarding Root Root is always a caller As a caller it needs to save on the stack: Any arguments and temporaries needed after calling the callee Arguments are given as the program is lauched Restore from the stack after calling the callee Root has no return address to save Chapter 2 Instructions: Language of the Computer 77

78 Calling Conventions regarding Leaf Procedures A leaf procedure is a callee A callee needs to save on the stack: Any saved registers it needs to use for computation Restore from the stack before returning the control back to the caller A callee needs to restore the following registers before returning the control back to the caller Global pointer register Frame pointer register Stack pointer register Chapter 2 Instructions: Language of the Computer 78

79 Leaf Procedure Example C code: int leaf_example (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; } Arguments g,, j in \$a0,, \$a3 f in \$s0 The procedure needs to save \$s0 on stack before using it Result in \$v0 Chapter 2 Instructions: Language of the Computer 79

80 Leaf Procedure Example MIPS code: leaf_example: addi \$sp, \$sp, -4 sw \$s0, 0(\$sp) add \$t0, \$a0, \$a1 add \$t1, \$a2, \$a3 sub \$s0, \$t0, \$t1 add \$v0, \$s0, \$zero lw \$s0, 0(\$sp) addi \$sp, \$sp, 4 jr \$ra Save \$s0 on stack Procedure body Result Restore \$s0 Return Chapter 2 Instructions: Language of the Computer 80

81 Stack Contents Before the call During the call After the call Chapter 2 Instructions: Language of the Computer 81

82 String Copy Example C code (naïve): Null-terminated string void strcpy (char x[], char y[]) { int i; i = 0; while ((x[i]=y[i])!='\0') i += 1; } Addresses of x, y in \$a0, \$a1 i in \$s0 Chapter 2 Instructions: Language of the Computer 82

83 String Copy Example MIPS code: strcpy: addi \$sp, \$sp, -4 # adjust stack for 1 item sw \$s0, 0(\$sp) # save \$s0 add \$s0, \$zero, \$zero # i = 0 L1: add \$t1, \$s0, \$a1 # addr of y[i] in \$t1 lbu \$t2, 0(\$t1) # \$t2 = y[i] add \$t3, \$s0, \$a0 # addr of x[i] in \$t3 sb \$t2, 0(\$t3) # x[i] = y[i] beq \$t2, \$zero, L2 # exit loop if y[i] == 0 addi \$s0, \$s0, 1 # i = i + 1 j L1 # next iteration of loop L2: lw \$s0, 0(\$sp) # restore saved \$s0 addi \$sp, \$sp, 4 # pop 1 item from stack jr \$ra # and return Chapter 2 Instructions: Language of the Computer 83

84 Non-Leaf Procedures Non-leaf procedure is both a caller and a callee As a caller it needs to save on the stack: Its return address, and any arguments and temporaries needed after calling the callee Restore from the stack after calling the callee As a callee it needs to restore the values of the following registers before returning Saved register, global pointer register, frame pointer register, stack pointer register Chapter 2 Instructions: Language of the Computer 84

85 Non-Leaf Procedure Example Factorial n! = (n-1) n C code: int fact (int n) { if (n < 2) return 1; else return n * fact(n - 1); } Argument n in \$a0 Result in \$v0 Chapter 2 Instructions: Language of the Computer 85

86 Non-Leaf Procedure Example MIPS code: fact:addi \$sp, \$sp, -8 # adjust stack for 2 items sw \$ra, 4(\$sp) # save return address sw \$a0, 0(\$sp) # save argument slti \$t0, \$a0, 2 # test for n < 2 beq \$t0, \$zero, L1 # if (n>=2), jump to L1 addi \$v0, \$zero, 1 # if (n<2), result is 1 addi \$sp, \$sp, 8 # pop 2 items from stack jr \$ra # and return L1: addi \$a0, \$a0, -1 # else decrement n jal fact # recursive call nop lw \$a0, 0(\$sp) # restore original n lw \$ra, 4(\$sp) # and return address addi \$sp, \$sp, 8 # pop 2 items from stack mul \$v0, \$a0, \$v0 # multiply to get result jr \$ra # and return Chapter 2 Instructions: Language of the Computer 86

87 A C Sort Example to Put It All Chapter 2.13 Chapter 2 Instructions: Language of the Computer 87

88 C Sort Example Illustrates use of assembly instructions for a C sinking sort function Sort a sequence into a non-decreasing order Swap procedure (leaf) void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } v in \$a0, k in \$a1, temp in \$t A C Sort Example to Put It All Together Chapter 2 Instructions: Language of the Computer 88

89 The Procedure Swap swap: sll \$t1, \$a1, 2 # \$t1 = k * 4 add \$t1, \$a0, \$t1 # \$t1 = v+(k*4) # (address of v[k]) lw \$t0, 0(\$t1) # \$t0 (temp) = v[k] lw \$t2, 4(\$t1) # \$t2 = v[k+1] sw \$t2, 0(\$t1) # v[k] = \$t2 (v[k+1]) sw \$t0, 4(\$t1) # v[k+1] = \$t0 (temp) jr \$ra # return to calling routine Chapter 2 Instructions: Language of the Computer 89

90 The Sort Procedure in C Non-leaf (calls swap) void sort (int v[], int n) { int i, j; for (i = 0; i < n; i += 1) { for (j = i 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v,j); } } } v in \$a0, n in \$a1, i in \$s0, j in \$s1 Use \$s2 and \$s3 to save v and n Chapter 2 Instructions: Language of the Computer 90

91 The Full Procedure sort: addi \$sp,\$sp, 20 # make room on stack for 5 registers sw \$ra,16(\$sp) # save \$ra on stack sw \$s3,12(\$sp) # save \$s3 on stack sw \$s2, 8(\$sp) # save \$s2 on stack sw \$s1, 4(\$sp) # save \$s1 on stack sw \$s0, 0(\$sp) # save \$s0 on stack # procedure body (see next slide) exit1: lw \$s0, 0(\$sp) # restore \$s0 from stack lw \$s1, 4(\$sp) # restore \$s1 from stack lw \$s2, 8(\$sp) # restore \$s2 from stack lw \$s3,12(\$sp) # restore \$s3 from stack lw \$ra,16(\$sp) # restore \$ra from stack addi \$sp,\$sp, 20 # restore stack pointer jr \$ra # return to calling routine Chapter 2 Instructions: Language of the Computer 91

93 Addressing Mode Summary Chapter 2 Instructions: Language of the Computer 93

94 Delay slot Delay slot is an instruction slot that gets executed without the effects of a preceding instruction When an instruction is executed, the following instruction is put into the delay slot In hardware and some simulators, the instruction following jump and branch instructions is always executed Add nop after the jump and branch instructions in your lab to simply coding Chapter 2 Instructions: Language of the Computer 94

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