CISC 662 Graduate Computer Architecture. Lecture 4 - ISA
|
|
- Valentine Bradley
- 5 years ago
- Views:
Transcription
1 CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture, 4th edition ---- Additional teaching material from: Jelena Mirkovic (U Del) and John Kubiatowicz (UC Berkeley)
2 MIPS ISA
3 In a CPU PC 4 ALU Instruction cache IM NPC IR Reg A B Zero? M U X M U X ALU opcode Cond ALU Output M U X Data cache DM Cond LMD M U X Sign extend Imm opcode To main memory To main memory
4 (vonneumann) Processor Organization Control needs to: input instructions from Memory issue signals to control the information flow between the Datapath components and to control what operations they perform control instruction sequencing CPU Control Datapath Memory Fetch Devices Input Output Datapath needs to have the: components the functional units and Exec storage (e.g., register file) needed to execute instructions Decode interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory
5 MIPS R3000 Instruction Set Architecture (ISA) Instruction Categories Computational Load/Store Jump and Branch Floating Point - coprocessor Memory Management Special Registers: all bits wide R0 - R31 PC HI LO 3 Instruction Formats: all bits wide OP OP OP rs rt rd sa funct rs rt immediate jump target R format I format J format
6 MIPS Register Convention Name $zero $at $v0 - $v1 $a0 - $a3 $t0 - $t7 $s0 - $s7 $t8 - $t9 $gp $sp $fp $ra Register Number Usage constant 0 (hardware) reserved for assembler returned values arguments temporaries saved values temporaries global pointer stack pointer frame pointer return addr (hardware) Preserve on call? n.a. n.a. no yes no yes no yes yes yes yes
7 MIPS Register File Holds thirty-two -bit registers Two read ports and One write port Registers are Faster than main memory src1 addr src2 addr dst addr write data - But register files with more locations are slower (e.g., a 64 word file could be as much as 50% slower than a word file) Register File bits locations - Read/write port increase impacts speed quadratically Easier for a compiler to use write control - e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack Can hold variables so that - code density improves (since register are named with fewer bits than a memory location) src1 data src2 data
8 MIPS Arithmetic Instructions
9 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu, neg mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu A B zero ovf 1 1 ALU 4 m (operation) result With special handling for sign extend addi, addiu andi, ori, xori, slti, sltiu zero extend lbu, addiu, sltiu no overflow detected addu, addiu, subu, multu, divu, sltiu, sltu
10 MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction fits in bits and specifies exactly three operands destination source1 op source2 Those operands are all contained in the datapath s register file ($t0,$s1,$s2) indicated by $ Operand order is fixed (destination first)
11 MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction fits in bits and specifies exactly three operands destination source1 op source2 Operand order is fixed (destination first) Those operands are all contained in the datapath s register file ($t0,$s1,$s2) indicated by $
12 Example C code: a = a+b+c; MIPS code: a: $s0 b: $s1 c: $s2 add $t0, $s1, $s2 add $s0, $s0, $t0
13 Machine Language - Add Instruction Instructions, like registers and words of data, are bits long Arithmetic Instruction Format (R format): add $t0, $s1, $s2 op rs rt rd shamt funct op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode
14 Example Consider the following AL instruction: add $t0, $s1, $s2 What is the equivalent ML instruction? Some help: add is an R-format instruction What is the structure of an R-format instructions: Op-code rs rt rd shamt funct
15 Example con t Consider the following AL instruction: add $t0, $s1, $s2 On MIPS processors: $t0 is mapped into the number $s1 is mapped into the number $s2 is mapped into the number and is a source/destination and is a source/destination and is a source/destination Op-code rs rt rd shamt funct
16 Logical Operations MIPS code: sll $t2, $s0, 4 # $t2 = $s0 << 4 bits Q: What format does the sll instruction have? R-format OP rs rt rd sa funct R format OP OP rs rt immediate jump target I format J format Op-code rs rt rd shamt funct
17 AND / OR Let s assume that: AL: $t2 = $t1 = and $t0, $t1, $t2 $t0 = AND mask since it conceals some bits Let s assume that: $t2 = $t1 = AL: or $t0, $t1, $t2 $t0 =
18 MIPS Immediate Instructions Small constants are used often in typical code Possible approaches? put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants! addi $sp, $sp, 4 #$sp = $sp + 4 slti $t0, $s2, 15 #$t0 = 1 if $s2<15 Machine format (I format): op rs rt 16 bit immediate I format The constant is kept inside the instruction itself! Immediate format limits values to the range to -2 15
19 Addi addi is an immediate instruction Q: Why are immediate instructions so important? A: The sum of a constant to a variable is a common operation. Immediate instructions make this common case faster.
20 Load-Store
21 And if we need more data How do we represent complex data structures (i.e., array, structure) in assembly? We have a reduced number of registers!!!! How many? Memory can contain millions of data elements register address address address address address data data data data data Memory We need instructions that transfer data from and to the memory data transfer instructions
22 Memory Representation We think so It is so. address address address address address data data data data data bits Memory large, single-dimension array Memory addresses indexes to this array To access data in memory or put data in memory we have two instructions: load and store
23 MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw sw $t0, 4($s3) #load word from memory $t0, 8($s3) #store word to memory The data is loaded into (lw) or stored from (sw) a register in the register file a 5 bit address The memory address a bit address is formed by adding the contents of the base address register to the offset value A 16-bit field meaning access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or,768 bytes) of the address in the base register Note that the offset can be positive or negative
24 Machine Language - Load Instruction Load/Store Instruction Format (I format): lw $t0, 24($s2) op rs rt 16 bit offset $s2 = Memory 0xf f f f f f f f = 0x120040ac $t0 $s2 0x data 0x120040ac 0x c 0x x x word address (hex)
25 Loading and Storing Bytes MIPS provides special instructions to move bytes lb sb $t0, 1($s3) #load byte from memory $t0, 6($s3) #store byte to memory op rs rt 16 bit offset What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8 bits of the destination register - what happens to the other bits in the register? store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory - what happens to the other bits in the memory word?
26 Example: Load C code: int A [100]; int g; int h; g = h + A [5]; To write the equivalent MIPS code: base address of A is in $s3 g is assigned to $s1 h is assigned to $s2 Write the MIPS code: lw $t0, 20($s3) # the temp register $t0 gets A [5 ] add $s1, $s2, $t0 # g = h + $t0 Why 20? 20 words or bytes?
27 Example: Store C code: int A [100]; int g; int h; A [12] = h + A [8]; Assign variables to registers: base address of A is in $s3 h is assigned to $s2 lw $t0, ($s3) # the temp register $t0 gets A [ 8 ] add $t0, $s2, $t0 # $t0= h + $t0 sw $t0, 48($s3) # store the temp register $t0 in A [12]
28 Example: Store C code: int A [100]; int g; Int h; A [12] = A [8]; 100 is a constant Assign variables to registers: base address of A is in $s3 lw $t0, ($s3) # the temp register $t0 gets A [ 8 ] addi $t0, $t0, 100 # $t0= $t0 sw $t0, 48($s3) # store the temp register $t0 in A [12]
29 Control Flow Instructions
30 MIPS Control Flow Instructions MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0 $s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 Lbl1:... Instruction Format (I format): op rs rt 16 bit offset How is the branch destination address specified?
31 Specifying Branch Destinations Use a register (like in lw and sw) added to the 16-bit offset which register? Instruction Address Register (the PC) - its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction limits the branch distance to to instructions from the (instruction after the) branch instruction, but most branches are local anyway from the low order 16 bits of the branch instruction sign-extend 16 offset 00 PC 4 Add Add? branch dst address
32 More Branch Instructions We have beq, bne, but what about other kinds of brances (e.g., branch-if-less-than)? For this, we need yet another instruction, slt Set on less than instruction: slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1 else # $t0 = 0 Instruction format (R format): op rs rt rd funct 2
33 More Branch Instructions, Con t Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions less than blt $s1, $s2, Label slt $at, $s1, $s2 #$at set to 1 if bne $at, $zero, Label # $s1 < $s2 less than or equal to greater than great than or equal to ble $s1, $s2, Label bgt $s1, $s2, Label bge $s1, $s2, Label Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler Its why the assembler needs a reserved register ($at)
34 Other Control Flow Instructions MIPS also has an unconditional branch instruction or jump instruction: j label #go to label Instruction Format (J Format): op 26-bit address from the low order 26 bits of the jump instruction PC
35 Aside: Branching Far Away What if the branch destination is further away than can be captured in 16 bits? The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1 becomes L2: bne j $s0, $s1, L2 L1
36 Converting C Code into AL (I) C code: if ( i == j) else f = g + h; f = g h; AL code: Assign variables to registers: i $s3 j $s4 f $s0 g $s1 h $s2 Do simple translations f. add $s0, $s1, $s2 # f = g + h g. sub $s0, $s1, $s2 # f = g - h Organize the translations bne $s3, $s4, ELSE f. j EXIT ELSE: g. EXIT:. Complete the code bne $s3, $s4, ELSE add $s0, $s1, $s2 # f = g + h j EXIT ELSE: sub $s0, $s1, $s2 # f = g - h EXIT:.
37 Converting C Code into AL (II) C code: while (save[i] = = k) i += 1; Convert the code in MIPS AL 1. Assign variables to registers: save $s 6 i $s 3 k $s 5 2. Do simple translations: a. compute address in memory for index i sll $t1, $s3, 2 # add = i * 4 = i << 2 b. load save[i] lw $t0, $t1($s6) c. increase i addi $s 3, $s 3, 1 # load save[i] # i+=1; 3. Organize the translations: LOOP: a. compute address in memory for index I b. b. load save[i] lw $t0, $t1($s6) # save[i[ <> k bne $t0, $s5, EXIT c. increase I j LOOP EXIT: 4. Complete the code: LOOP: sll $t1, $s3, 2 # add = i * 4 = i << 2 add $t1, $t1, $s6 lw $t0, 0($t1) # save[i[ <> k bne $t0, $s5, EXIT addi $s 3, $s 3, 1 # i+=1; j LOOP EXIT:
38 Converting AL into ML C code: while (save[i] == k) i += 1; Assembly code Loop: sll $t 1, $s 3, 2 # temp reg $t 1 = 4 * i where i $s 3 add $t 1, $t 1, $s 6 # $t 1 = address of save[i] lw $t 0, 0($t 1 ) # temp reg $t 0 = save[i] bne $t 0, $s 6, Exit # go to Exit if save[i] <> k addi $s 3, $s 3, 1 # increment I j Loop Exit: Write the equivalent ML instructions for the MIPS code above. The code is located in the text segment of the memory starting from 0x800000
39 : bne statement jumps to = * 4 Note that PC points always to the next instruction 80020: j instruction uses the full address x 4 = 80000
40 MIPS Review
41 MIPS Organization So Far src1 addr 5 src2 addr 5 dst addr 5 write data Processor Register File registers ($zero - $ra) bits src1 data src2 data read/write addr Memory words Exec branch offset PC Add 4 Fetch PC = PC+4 Decode Add ALU read data write data byte address (big Endian) bits word address (binary)
42 MIPS ISA So Far Category Arithmetic (R & I format) add subtract Instr add immediate or immediate Op Code 0 and 0 and Example add $s1, $s2, $s3 sub $s1, $s2, $s3 addi $s1, $s2, 6 ori $s1, $s2, 6 Meaning $s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 6 $s1 = $s2 v 6 Data Transfer (I format) load word store word load byte store byte load upper imm lw $s1, 24($s2) sw $s1, 24($s2) lb $s1, 25($s2) sb $s1, 25($s2) lui $s1, 6 $s1 = Memory($s2+24) Memory($s2+24) = $s1 $s1 = Memory($s2+25) Memory($s2+25) = $s1 $s1 = 6 * 2 16 Cond. Branch (I & R format) Uncond. Jump (J & R format) br on equal br on not equal set on less than set on less than immediate jump jump register jump and link and and 8 3 beq $s1, $s2, L bne $s1, $s2, L slt $s1, $s2, $s3 slti $s1, $s2, 6 j 2500 jr $t1 jal 2500 if ($s1==$s2) go to L if ($s1!=$s2) go to L if ($s2<$s3) $s1=1 else $s1=0 if ($s2<6) $s1=1 else $s1=0 go to go to $t1 go to 10000; $ra=pc+4
43 MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions -bits small number of instruction formats opcode always the first 6 bits Good design demands good compromises three instruction formats Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands
44 Review of MIPS Operand Addressing Modes Register addressing operand is in a register op rs rt rd funct Register Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction base register Register relative (indirect) with Pseudo-direct with 0($a0) addr($zero) word operand op rs rt offset Memory word or byte operand Immediate addressing operand is a 16-bit constant contained within the instruction op rs rt operand
45 Review of MIPS Instruction Addressing Modes PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction op rs rt offset Program Counter (PC) Memory branch destination instruction Pseudo-direct addressing instruction address is the 26- bit constant contained within the instruction concatenated with the upper 4 bits of the PC op jump address Program Counter (PC) Memory jump destination instruction
46 Next Deadlines Week Date Topics Reading assigned Quiz 1 Sep 4 Lec01 - Introduction Chap 1; App B 2 Sep 9 Lec02 Performance Q1 2 Sep 11 Lec03 ISAs and Role of Compilers App A1-A6 3 Sep 16 Lec04 - MIPS Overview 3 Sep 18 Lec05 Pipeline Q2 4 Sep 23 Lec06 - Hazards 4 Sep 25 Lec07 Multi-cycles App A.7; Chap 2 Sep 29 Homework 1 due 5 Sep 30 Homework review Q3
CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationComputer Organization MIPS ISA
CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE 232 MIPS ISA 1 (vonneumann) Processor Organization
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationCourse Administration
Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu
More informationChapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationChapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.
Chapter 2 Instructions: Language of the Computer HW#1: 1.3 all, 1.4 all, 1.6.1, 1.14.4, 1.14.5, 1.14.6, 1.15.1, and 1.15.4 Due date: one week. Practice: 1.5 all, 1.6 all, 1.10 all, 1.11 all, 1.14 all,
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationInstructions: Language of the Computer
Instructions: Language of the Computer Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationCS31001 COMPUTER ORGANIZATION AND ARCHITECTURE. Debdeep Mukhopadhyay, CSE, IIT Kharagpur. Instructions and Addressing
CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE Debdeep Mukhopadhyay, CSE, IIT Kharagpur Instructions and Addressing 1 ISA vs. Microarchitecture An ISA or Instruction Set Architecture describes the aspects
More informationCENG3420 L03: Instruction Set Architecture
CENG3420 L03: Instruction Set Architecture Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 31, 2018) Spring 2018 1 / 49 Overview Introduction Arithmetic & Logical Instructions Data Transfer Instructions
More informationCS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,
More informationMIPS Memory Access Instructions
MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory The data is loaded into (lw)
More information101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009
101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationCOMPSCI 313 S Computer Organization. 7 MIPS Instruction Set
COMPSCI 313 S2 2018 Computer Organization 7 MIPS Instruction Set Agenda & Reading MIPS instruction set MIPS I-format instructions MIPS R-format instructions 2 7.1 MIPS Instruction Set MIPS Instruction
More informationComputer Architecture. The Language of the Machine
Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers
More informationMIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions
Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register
More informationInstruction Set Architecture part 1 (Introduction) Mehran Rezaei
Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a
More informationIntroduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department
More informationControl Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary
Control Instructions Computer Organization Architectures for Embedded Computing Thursday, 26 September 2013 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition,
More informationControl Instructions
Control Instructions Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class Instruction Set
More informationComputer Architecture. MIPS Instruction Set Architecture
Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design
More informationCS3350B Computer Architecture MIPS Introduction
CS3350B Computer Architecture MIPS Introduction Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada Thursday January
More informationOverview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)
Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into
More informationMIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support
Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationCS222: MIPS Instruction Set
CS222: MIPS Instruction Set Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Previous Introduction to MIPS Instruction Set MIPS Arithmetic's Register Vs Memory, Registers
More informationComputer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology
Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.
More informationMark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA
EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring MIPS Intro
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L09.1 Smith Spring 2008 MIPS
More informationChapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )
Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise
More informationTopic Notes: MIPS Instruction Set Architecture
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
More informationToday s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.
Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic
More informationAnnouncements HW1 is due on this Friday (Sept 12th) Appendix A is very helpful to HW1. Check out system calls
Announcements HW1 is due on this Friday (Sept 12 th ) Appendix A is very helpful to HW1. Check out system calls on Page A-48. Ask TA (Liquan chen: liquan@ece.rutgers.edu) about homework related questions.
More informationECE260: Fundamentals of Computer Engineering
MIPS Instruction Set James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy MIPS Registers MIPS
More informationReview: MIPS Organization
1 MIPS Arithmetic Review: MIPS Organization Processor Memory src1 addr 5 src2 addr 5 dst addr 5 write data Register File registers ($zero - $ra) bits src1 data src2 data read/write addr 1 1100 2 30 words
More informationMIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
More information5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers
CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language
More information1 5. Addressing Modes COMP2611 Fall 2015 Instruction: Language of the Computer
1 5. Addressing Modes MIPS Addressing Modes 2 Addressing takes care of where to find data instruction We have seen, so far three addressing modes of MIPS (to find data): 1. Immediate addressing: provides
More informationRecap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011
CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationCS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 th The Hardware/Software Interface Edition Chapter 2 Instructions: Language of the Computer 2.1 Introduction Instruction Set The repertoire of instructions of a computer
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationECE260: Fundamentals of Computer Engineering
MIPS Instruction Set James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy MIPS Registers MIPS
More informationRechnerstrukturen. Chapter 2. Instructions: Language of the Computer
182.690 Rechnerstrukturen Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
More informationLecture 4: MIPS Instruction Set
Lecture 4: MIPS Instruction Set No class on Tuesday Today s topic: MIPS instructions Code examples 1 Instruction Set Understanding the language of the hardware is key to understanding the hardware/software
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationCS/COE1541: Introduction to Computer Architecture
CS/COE1541: Introduction to Computer Architecture Dept. of Computer Science University of Pittsburgh http://www.cs.pitt.edu/~melhem/courses/1541p/index.html 1 Computer Architecture? Application pull Operating
More informationProcessor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4
Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.
More informationMACHINE LANGUAGE. To work with the machine, we need a translator.
LECTURE 2 Assembly MACHINE LANGUAGE As humans, communicating with a machine is a tedious task. We can t, for example, just say add this number and that number and store the result here. Computers have
More informationChapter 2: Instructions:
Chapter 2: Instructions: Language of the Computer Computer Architecture CS-3511-2 1 Instructions: To command a computer s hardware you must speak it s language The computer s language is called instruction
More informationSystems Architecture I
Systems Architecture I Topics Assemblers, Linkers, and Loaders * Alternative Instruction Sets ** *This lecture was derived from material in the text (sec. 3.8-3.9). **This lecture was derived from material
More informationMIPS (SPIM) Assembler Syntax
MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin
More informationInstruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
More informationMIPS Instruction Set
MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central
More informationConcocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von
More informationInstruction Set Design and Architecture
Instruction Set Design and Architecture COE608: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Computer
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to
More informationEEC 581 Computer Architecture Lecture 1 Review MIPS
EEC 581 Computer Architecture Lecture 1 Review MIPS 1 Supercomputing: Suddenly Fancy 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control
More informationChapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance
Chapter 1 Computer Abstractions and Technology Lesson 3: Understanding Performance Manufacturing ICs 1.7 Real Stuff: The AMD Opteron X4 Yield: proportion of working dies per wafer Chapter 1 Computer Abstractions
More informationCSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationChapter 2. Instructions:
Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined
More informationInstructions: MIPS arithmetic. MIPS arithmetic. Chapter 3 : MIPS Downloaded from:
Instructions: Chapter 3 : MIPS Downloaded from: http://www.cs.umr.edu/~bsiever/cs234/ Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive
More informationCSE 141 Computer Architecture Spring Lecture 3 Instruction Set Architecute. Course Schedule. Announcements
CSE141: Introduction to Computer Architecture CSE 141 Computer Architecture Spring 2005 Lecture 3 Instruction Set Architecute Pramod V. Argade April 4, 2005 Instructor: TAs: Pramod V. Argade (p2argade@cs.ucsd.edu)
More informationChapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1
Chapter 3 MIPS Assembly Language Ó1998 Morgan Kaufmann Publishers 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive
More informationM2 Instruction Set Architecture
M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine
More informationUnsigned Binary Integers
Unsigned Binary Integers Given an n-bit number x x n 1 n 2 1 0 n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + + 1 2 3 + 0
More informationUnsigned Binary Integers
Unsigned Binary Integers Given an n-bit number x x n 1 n 2 1 0 n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + + 1 2 3 + 0
More informationLectures 3-4: MIPS instructions
Lectures 3-4: MIPS instructions Motivation Learn how a processor s native language looks like Discover the most important software-hardware interface MIPS Microprocessor without Interlocked Pipeline Stages
More informationCENG 3420 Lecture 06: Datapath
CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference
More informationENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local
More informationMIPS Instruction Reference
Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly
More informationEN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design
EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown
More informationF. Appendix 6 MIPS Instruction Reference
F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them
More informationBranch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015
Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative
More informationComputer Architecture Instruction Set Architecture part 2. Mehran Rezaei
Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter
More informationChapter 2. Instruction Set Architecture (ISA)
Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record
More informationA General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction
page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches
More informationArithmetic for Computers
MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.
More informationReview of instruction set architectures
Review of instruction set architectures Outline ISA and Assembly Language RISC vs. CISC Instruction Set Definition (MIPS) 2 ISA and assembly language Assembly language ISA Machine language 3 Assembly language
More informationINSTRUCTION SET COMPARISONS
INSTRUCTION SET COMPARISONS MIPS SPARC MOTOROLA REGISTERS: INTEGER 32 FIXED WINDOWS 32 FIXED FP SEPARATE SEPARATE SHARED BRANCHES: CONDITION CODES NO YES NO COMPARE & BR. YES NO YES A=B COMP. & BR. YES
More informationCS 351 Exam 2 Mon. 11/2/2015
CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front
More information