CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

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1 CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture, 4th edition ---- Additional teaching material from: Jelena Mirkovic (U Del) and John Kubiatowicz (UC Berkeley)

2 MIPS ISA

3 In a CPU PC 4 ALU Instruction cache IM NPC IR Reg A B Zero? M U X M U X ALU opcode Cond ALU Output M U X Data cache DM Cond LMD M U X Sign extend Imm opcode To main memory To main memory

4 (vonneumann) Processor Organization Control needs to: input instructions from Memory issue signals to control the information flow between the Datapath components and to control what operations they perform control instruction sequencing CPU Control Datapath Memory Fetch Devices Input Output Datapath needs to have the: components the functional units and Exec storage (e.g., register file) needed to execute instructions Decode interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory

5 MIPS R3000 Instruction Set Architecture (ISA) Instruction Categories Computational Load/Store Jump and Branch Floating Point - coprocessor Memory Management Special Registers: all bits wide R0 - R31 PC HI LO 3 Instruction Formats: all bits wide OP OP OP rs rt rd sa funct rs rt immediate jump target R format I format J format

6 MIPS Register Convention Name $zero $at $v0 - $v1 $a0 - $a3 $t0 - $t7 $s0 - $s7 $t8 - $t9 $gp $sp $fp $ra Register Number Usage constant 0 (hardware) reserved for assembler returned values arguments temporaries saved values temporaries global pointer stack pointer frame pointer return addr (hardware) Preserve on call? n.a. n.a. no yes no yes no yes yes yes yes

7 MIPS Register File Holds thirty-two -bit registers Two read ports and One write port Registers are Faster than main memory src1 addr src2 addr dst addr write data - But register files with more locations are slower (e.g., a 64 word file could be as much as 50% slower than a word file) Register File bits locations - Read/write port increase impacts speed quadratically Easier for a compiler to use write control - e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack Can hold variables so that - code density improves (since register are named with fewer bits than a memory location) src1 data src2 data

8 MIPS Arithmetic Instructions

9 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu, neg mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu A B zero ovf 1 1 ALU 4 m (operation) result With special handling for sign extend addi, addiu andi, ori, xori, slti, sltiu zero extend lbu, addiu, sltiu no overflow detected addu, addiu, subu, multu, divu, sltiu, sltu

10 MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction fits in bits and specifies exactly three operands destination source1 op source2 Those operands are all contained in the datapath s register file ($t0,$s1,$s2) indicated by $ Operand order is fixed (destination first)

11 MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction fits in bits and specifies exactly three operands destination source1 op source2 Operand order is fixed (destination first) Those operands are all contained in the datapath s register file ($t0,$s1,$s2) indicated by $

12 Example C code: a = a+b+c; MIPS code: a: $s0 b: $s1 c: $s2 add $t0, $s1, $s2 add $s0, $s0, $t0

13 Machine Language - Add Instruction Instructions, like registers and words of data, are bits long Arithmetic Instruction Format (R format): add $t0, $s1, $s2 op rs rt rd shamt funct op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode

14 Example Consider the following AL instruction: add $t0, $s1, $s2 What is the equivalent ML instruction? Some help: add is an R-format instruction What is the structure of an R-format instructions: Op-code rs rt rd shamt funct

15 Example con t Consider the following AL instruction: add $t0, $s1, $s2 On MIPS processors: $t0 is mapped into the number $s1 is mapped into the number $s2 is mapped into the number and is a source/destination and is a source/destination and is a source/destination Op-code rs rt rd shamt funct

16 Logical Operations MIPS code: sll $t2, $s0, 4 # $t2 = $s0 << 4 bits Q: What format does the sll instruction have? R-format OP rs rt rd sa funct R format OP OP rs rt immediate jump target I format J format Op-code rs rt rd shamt funct

17 AND / OR Let s assume that: AL: $t2 = $t1 = and $t0, $t1, $t2 $t0 = AND mask since it conceals some bits Let s assume that: $t2 = $t1 = AL: or $t0, $t1, $t2 $t0 =

18 MIPS Immediate Instructions Small constants are used often in typical code Possible approaches? put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants! addi $sp, $sp, 4 #$sp = $sp + 4 slti $t0, $s2, 15 #$t0 = 1 if $s2<15 Machine format (I format): op rs rt 16 bit immediate I format The constant is kept inside the instruction itself! Immediate format limits values to the range to -2 15

19 Addi addi is an immediate instruction Q: Why are immediate instructions so important? A: The sum of a constant to a variable is a common operation. Immediate instructions make this common case faster.

20 Load-Store

21 And if we need more data How do we represent complex data structures (i.e., array, structure) in assembly? We have a reduced number of registers!!!! How many? Memory can contain millions of data elements register address address address address address data data data data data Memory We need instructions that transfer data from and to the memory data transfer instructions

22 Memory Representation We think so It is so. address address address address address data data data data data bits Memory large, single-dimension array Memory addresses indexes to this array To access data in memory or put data in memory we have two instructions: load and store

23 MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw sw $t0, 4($s3) #load word from memory $t0, 8($s3) #store word to memory The data is loaded into (lw) or stored from (sw) a register in the register file a 5 bit address The memory address a bit address is formed by adding the contents of the base address register to the offset value A 16-bit field meaning access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or,768 bytes) of the address in the base register Note that the offset can be positive or negative

24 Machine Language - Load Instruction Load/Store Instruction Format (I format): lw $t0, 24($s2) op rs rt 16 bit offset $s2 = Memory 0xf f f f f f f f = 0x120040ac $t0 $s2 0x data 0x120040ac 0x c 0x x x word address (hex)

25 Loading and Storing Bytes MIPS provides special instructions to move bytes lb sb $t0, 1($s3) #load byte from memory $t0, 6($s3) #store byte to memory op rs rt 16 bit offset What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8 bits of the destination register - what happens to the other bits in the register? store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory - what happens to the other bits in the memory word?

26 Example: Load C code: int A [100]; int g; int h; g = h + A [5]; To write the equivalent MIPS code: base address of A is in $s3 g is assigned to $s1 h is assigned to $s2 Write the MIPS code: lw $t0, 20($s3) # the temp register $t0 gets A [5 ] add $s1, $s2, $t0 # g = h + $t0 Why 20? 20 words or bytes?

27 Example: Store C code: int A [100]; int g; int h; A [12] = h + A [8]; Assign variables to registers: base address of A is in $s3 h is assigned to $s2 lw $t0, ($s3) # the temp register $t0 gets A [ 8 ] add $t0, $s2, $t0 # $t0= h + $t0 sw $t0, 48($s3) # store the temp register $t0 in A [12]

28 Example: Store C code: int A [100]; int g; Int h; A [12] = A [8]; 100 is a constant Assign variables to registers: base address of A is in $s3 lw $t0, ($s3) # the temp register $t0 gets A [ 8 ] addi $t0, $t0, 100 # $t0= $t0 sw $t0, 48($s3) # store the temp register $t0 in A [12]

29 Control Flow Instructions

30 MIPS Control Flow Instructions MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0 $s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 Lbl1:... Instruction Format (I format): op rs rt 16 bit offset How is the branch destination address specified?

31 Specifying Branch Destinations Use a register (like in lw and sw) added to the 16-bit offset which register? Instruction Address Register (the PC) - its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction limits the branch distance to to instructions from the (instruction after the) branch instruction, but most branches are local anyway from the low order 16 bits of the branch instruction sign-extend 16 offset 00 PC 4 Add Add? branch dst address

32 More Branch Instructions We have beq, bne, but what about other kinds of brances (e.g., branch-if-less-than)? For this, we need yet another instruction, slt Set on less than instruction: slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1 else # $t0 = 0 Instruction format (R format): op rs rt rd funct 2

33 More Branch Instructions, Con t Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions less than blt $s1, $s2, Label slt $at, $s1, $s2 #$at set to 1 if bne $at, $zero, Label # $s1 < $s2 less than or equal to greater than great than or equal to ble $s1, $s2, Label bgt $s1, $s2, Label bge $s1, $s2, Label Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler Its why the assembler needs a reserved register ($at)

34 Other Control Flow Instructions MIPS also has an unconditional branch instruction or jump instruction: j label #go to label Instruction Format (J Format): op 26-bit address from the low order 26 bits of the jump instruction PC

35 Aside: Branching Far Away What if the branch destination is further away than can be captured in 16 bits? The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1 becomes L2: bne j $s0, $s1, L2 L1

36 Converting C Code into AL (I) C code: if ( i == j) else f = g + h; f = g h; AL code: Assign variables to registers: i $s3 j $s4 f $s0 g $s1 h $s2 Do simple translations f. add $s0, $s1, $s2 # f = g + h g. sub $s0, $s1, $s2 # f = g - h Organize the translations bne $s3, $s4, ELSE f. j EXIT ELSE: g. EXIT:. Complete the code bne $s3, $s4, ELSE add $s0, $s1, $s2 # f = g + h j EXIT ELSE: sub $s0, $s1, $s2 # f = g - h EXIT:.

37 Converting C Code into AL (II) C code: while (save[i] = = k) i += 1; Convert the code in MIPS AL 1. Assign variables to registers: save $s 6 i $s 3 k $s 5 2. Do simple translations: a. compute address in memory for index i sll $t1, $s3, 2 # add = i * 4 = i << 2 b. load save[i] lw $t0, $t1($s6) c. increase i addi $s 3, $s 3, 1 # load save[i] # i+=1; 3. Organize the translations: LOOP: a. compute address in memory for index I b. b. load save[i] lw $t0, $t1($s6) # save[i[ <> k bne $t0, $s5, EXIT c. increase I j LOOP EXIT: 4. Complete the code: LOOP: sll $t1, $s3, 2 # add = i * 4 = i << 2 add $t1, $t1, $s6 lw $t0, 0($t1) # save[i[ <> k bne $t0, $s5, EXIT addi $s 3, $s 3, 1 # i+=1; j LOOP EXIT:

38 Converting AL into ML C code: while (save[i] == k) i += 1; Assembly code Loop: sll $t 1, $s 3, 2 # temp reg $t 1 = 4 * i where i $s 3 add $t 1, $t 1, $s 6 # $t 1 = address of save[i] lw $t 0, 0($t 1 ) # temp reg $t 0 = save[i] bne $t 0, $s 6, Exit # go to Exit if save[i] <> k addi $s 3, $s 3, 1 # increment I j Loop Exit: Write the equivalent ML instructions for the MIPS code above. The code is located in the text segment of the memory starting from 0x800000

39 : bne statement jumps to = * 4 Note that PC points always to the next instruction 80020: j instruction uses the full address x 4 = 80000

40 MIPS Review

41 MIPS Organization So Far src1 addr 5 src2 addr 5 dst addr 5 write data Processor Register File registers ($zero - $ra) bits src1 data src2 data read/write addr Memory words Exec branch offset PC Add 4 Fetch PC = PC+4 Decode Add ALU read data write data byte address (big Endian) bits word address (binary)

42 MIPS ISA So Far Category Arithmetic (R & I format) add subtract Instr add immediate or immediate Op Code 0 and 0 and Example add $s1, $s2, $s3 sub $s1, $s2, $s3 addi $s1, $s2, 6 ori $s1, $s2, 6 Meaning $s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 6 $s1 = $s2 v 6 Data Transfer (I format) load word store word load byte store byte load upper imm lw $s1, 24($s2) sw $s1, 24($s2) lb $s1, 25($s2) sb $s1, 25($s2) lui $s1, 6 $s1 = Memory($s2+24) Memory($s2+24) = $s1 $s1 = Memory($s2+25) Memory($s2+25) = $s1 $s1 = 6 * 2 16 Cond. Branch (I & R format) Uncond. Jump (J & R format) br on equal br on not equal set on less than set on less than immediate jump jump register jump and link and and 8 3 beq $s1, $s2, L bne $s1, $s2, L slt $s1, $s2, $s3 slti $s1, $s2, 6 j 2500 jr $t1 jal 2500 if ($s1==$s2) go to L if ($s1!=$s2) go to L if ($s2<$s3) $s1=1 else $s1=0 if ($s2<6) $s1=1 else $s1=0 go to go to $t1 go to 10000; $ra=pc+4

43 MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions -bits small number of instruction formats opcode always the first 6 bits Good design demands good compromises three instruction formats Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands

44 Review of MIPS Operand Addressing Modes Register addressing operand is in a register op rs rt rd funct Register Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction base register Register relative (indirect) with Pseudo-direct with 0($a0) addr($zero) word operand op rs rt offset Memory word or byte operand Immediate addressing operand is a 16-bit constant contained within the instruction op rs rt operand

45 Review of MIPS Instruction Addressing Modes PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction op rs rt offset Program Counter (PC) Memory branch destination instruction Pseudo-direct addressing instruction address is the 26- bit constant contained within the instruction concatenated with the upper 4 bits of the PC op jump address Program Counter (PC) Memory jump destination instruction

46 Next Deadlines Week Date Topics Reading assigned Quiz 1 Sep 4 Lec01 - Introduction Chap 1; App B 2 Sep 9 Lec02 Performance Q1 2 Sep 11 Lec03 ISAs and Role of Compilers App A1-A6 3 Sep 16 Lec04 - MIPS Overview 3 Sep 18 Lec05 Pipeline Q2 4 Sep 23 Lec06 - Hazards 4 Sep 25 Lec07 Multi-cycles App A.7; Chap 2 Sep 29 Homework 1 due 5 Sep 30 Homework review Q3

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