# LECTURE 2: INSTRUCTIONS

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1 LECTURE 2: INSTRUCTIONS Abridged version of Patterson & Hennessy (2013):Ch.2

2 Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers had very simple instruction sets Simplified implementation Many modern computers also have simple instruction sets 2.1 Introduction Chapter 2 Instructions: Language of the Computer 2

3 The MIPS Instruction Set Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies ( Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs See MIPS ISA Chapter 2 Instructions: Language of the Computer 3

4 Arithmetic Operations Add and subtract, three operands Two sources and one destination add a, b, c # a gets b + c All arithmetic operations have this form Design Principle 1: Simplicity favours regularity Regularity makes implementation simpler Simplicity enables higher performance at lower cost 2.2 Operations of the Computer Hardware Chapter 2 Instructions: Language of the Computer 4

5 Register Operands Arithmetic instructions use register operands MIPS has a bit register file Use for frequently accessed data Numbered 0 to bit data called a word Assembler names \$t0, \$t1,, \$t9 for temporary values \$s0, \$s1,, \$s7 for saved variables Design Principle 2: Smaller is faster c.f. main memory: millions of locations 2.3 Operands of the Computer Hardware Chapter 2 Instructions: Language of the Computer 5

6 Register Usage \$a0 \$a3: arguments (reg s 4 7) \$v0, \$v1: result values (reg s 2 and 3) \$t0 \$t9: temporaries Can be overwritten by callee \$s0 \$s7: saved Must be saved/restored by callee \$gp: global pointer for static data (reg 28) \$sp: stack pointer (reg 29) \$fp: frame pointer (reg 30) \$ra: return address (reg 31) Chapter 2 Instructions: Language of the Computer 6

7 Register Operand Example C code: f = (g + h) - (i + j); f,, j in \$s0,, \$s4 Compiled MIPS code: add \$t0, \$s1, \$s2 add \$t1, \$s3, \$s4 sub \$s0, \$t0, \$t1 Chapter 2 Instructions: Language of the Computer 7

8 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at least address of a word c.f. Little Endian: least-significant byte at least address Chapter 2 Instructions: Language of the Computer 8

9 Registers vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores More instructions to be executed Compiler must use registers for variables as much as possible Only spill to memory for less frequently used variables Register optimization is important! Chapter 2 Instructions: Language of the Computer 9

10 Immediate Operands Constant data specified in an instruction addi \$s3, \$s3, 4 No subtract immediate instruction Just use a negative constant addi \$s2, \$s1, -1 Design Principle 3: Make the common case fast Small constants are common Immediate operand avoids a load instruction Chapter 2 Instructions: Language of the Computer 10

11 Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, Regularity! Register numbers \$t0 \$t7 are reg s 8 15 \$t8 \$t9 are reg s \$s0 \$s7 are reg s Representing Instructions in the Computer Chapter 2 Instructions: Language of the Computer 11

12 MIPS R-format Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction fields op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (00000 for now) funct: function code (extends opcode) Chapter 2 Instructions: Language of the Computer 12

13 R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add \$t0, \$s1, \$s2 special \$s1 \$s2 \$t0 0 add = Chapter 2 Instructions: Language of the Computer 13

14 MIPS I-format Instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits Immediate arithmetic and load/store instructions rt: destination or source register number Constant: 2 15 to Address: offset added to base address in rs Design Principle 4: Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible Chapter 2 Instructions: Language of the Computer 14

15 Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative addressing Target address = PC + offset 4 PC already incremented by 4 by this time Chapter 2 Instructions: Language of the Computer 15

16 Jump Addressing Jump (j and jal) targets could be anywhere in text segment Encode full address in instruction op address 6 bits 26 bits (Pseudo)Direct jump addressing Target address = PC : (address 4) Chapter 2 Instructions: Language of the Computer 16

17 Target Addressing Example Loop code from earlier example Assume Loop at location Loop: sll \$t1, \$s3, add \$t1, \$t1, \$s lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit addi \$s3, \$s3, j Loop Exit: Chapter 2 Instructions: Language of the Computer 17

18 Branching Far Away If branch target is too far to encode with 16-bit offset, assembler rewrites the code Example beq \$s0,\$s1, L1 bne \$s0,\$s1, L2 j L1 L2: Chapter 2 Instructions: Language of the Computer 18

19 Addressing Mode Summary Chapter 2 Instructions: Language of the Computer 19

20 Compiling If Statements C code: if (i==j) f = g+h; else f = g-h; f, g, in \$s0, \$s1, Compiled MIPS code: bne \$s3, \$s4, Else add \$s0, \$s1, \$s2 j Exit Else: sub \$s0, \$s1, \$s2 Exit: Assembler calculates addresses Chapter 2 Instructions: Language of the Computer 20

21 Compiling Loop Statements C code: while (save[i] == k) i += 1; i in \$s3, k in \$s5, address of save in \$s6 Compiled MIPS code: Loop: sll \$t1, \$s3, 2 add \$t1, \$t1, \$s6 lw \$t0, 0(\$t1) bne \$t0, \$s5, Exit addi \$s3, \$s3, 1 j Loop Exit: Chapter 2 Instructions: Language of the Computer 21

22 Basic Blocks A basic block is a sequence of instructions with No embedded branches (except at end) No branch targets (except at beginning) A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks Chapter 2 Instructions: Language of the Computer 22

23 Stored Program Computers The BIG Picture Instructions represented in binary, just like data Instructions and data stored in memory Programs can operate on programs e.g., compilers, linkers, Binary compatibility allows compiled programs to work on different computers Standardized ISAs Chapter 2 Instructions: Language of the Computer 23

24 Memory Layout Text: program code Static data: global variables e.g., static variables in C, constant arrays and strings \$gp initialized to address allowing ±offsets into this segment Dynamic data: heap E.g., malloc in C, new in Java Stack: automatic storage Chapter 2 Instructions: Language of the Computer 24

25 Character Data Byte-encoded character sets ASCII: 128 characters 95 graphic, 33 control Latin-1: 256 characters ASCII, +96 more graphic characters Unicode: 32-bit character set 2.9 Communicating with People Used in Java, C++ wide characters, Most of the world s alphabets, plus symbols UTF-8, UTF-16: variable-length encodings Chapter 2 Instructions: Language of the Computer 25

26 Translation and Startup Many compilers produce object modules directly Static linking 2.12 Translating and Starting a Program Chapter 2 Instructions: Language of the Computer 26

27 Assembler Pseudoinstructions Most assembler instructions represent machine instructions one-to-one Pseudoinstructions: figments of the assembler s imagination move \$t0, \$t1 add \$t0, \$zero, \$t1 blt \$t0, \$t1, L slt \$at, \$t0, \$t1 bne \$at, \$zero, L \$at (register 1): assembler temporary Chapter 2 Instructions: Language of the Computer 27

28 Producing an Object Module Assembler (or compiler) translates program into machine instructions Provides information for building a complete program from the pieces Header: described contents of object module Text segment: translated instructions Static data segment: data allocated for the life of the program Relocation info: for contents that depend on absolute location of loaded program Symbol table: global definitions and external refs Debug info: for associating with source code Chapter 2 Instructions: Language of the Computer 28

29 Linking Object Modules Produces an executable image 1. Merges segments 2. Resolve labels (determine their addresses) 3. Patch location-dependent and external refs Could leave location dependencies for fixing by a relocating loader But with virtual memory, no need to do this Program can be loaded into absolute location in virtual memory space Chapter 2 Instructions: Language of the Computer 29

30 Loading a Program Load from image file on disk into memory 1. Read header to determine segment sizes 2. Create virtual address space 3. Copy text and initialized data into memory Or set page table entries so they can be faulted in 4. Set up arguments on stack 5. Initialize registers (including \$sp, \$fp, \$gp) 6. Jump to startup routine Copies arguments to \$a0, and calls main When main returns, do exit syscall Chapter 2 Instructions: Language of the Computer 30

31 Starting Java Applications Simple portable instruction set for the JVM Compiles bytecodes of hot methods into native code for host machine Interprets bytecodes Chapter 2 Instructions: Language of the Computer 31

32 C Sort Example Illustrates use of assembly instructions for a C bubble sort function Swap procedure (leaf) void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } v in \$a0, k in \$a1, temp in \$t A C Sort Example to Put It All Together Chapter 2 Instructions: Language of the Computer 32

33 The Procedure Swap swap: sll \$t1, \$a1, 2 # \$t1 = k * 4 add \$t1, \$a0, \$t1 # \$t1 = v+(k*4) # (address of v[k]) lw \$t0, 0(\$t1) # \$t0 (temp) = v[k] lw \$t2, 4(\$t1) # \$t2 = v[k+1] sw \$t2, 0(\$t1) # v[k] = \$t2 (v[k+1]) sw \$t0, 4(\$t1) # v[k+1] = \$t0 (temp) jr \$ra # return to calling routine Chapter 2 Instructions: Language of the Computer 33

34 The Sort Procedure in C Non-leaf (calls swap) void sort (int v[], int n) { int i, j; for (i = 0; i < n; i += 1) { for (j = i 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v,j); } } } v in \$a0, k in \$a1, i in \$s0, j in \$s1 Chapter 2 Instructions: Language of the Computer 34

35 The Procedure Body move \$s2, \$a0 # save \$a0 into \$s2 move \$s3, \$a1 # save \$a1 into \$s3 move \$s0, \$zero # i = 0 for1tst: slt \$t0, \$s0, \$s3 # \$t0 = 0 if \$s0 \$s3 (i n) beq \$t0, \$zero, exit1 # go to exit1 if \$s0 \$s3 (i n) addi \$s1, \$s0, 1 # j = i 1 for2tst: slti \$t0, \$s1, 0 # \$t0 = 1 if \$s1 < 0 (j < 0) bne \$t0, \$zero, exit2 # go to exit2 if \$s1 < 0 (j < 0) sll \$t1, \$s1, 2 # \$t1 = j * 4 add \$t2, \$s2, \$t1 # \$t2 = v + (j * 4) lw \$t3, 0(\$t2) # \$t3 = v[j] lw \$t4, 4(\$t2) # \$t4 = v[j + 1] slt \$t0, \$t4, \$t3 # \$t0 = 0 if \$t4 \$t3 beq \$t0, \$zero, exit2 # go to exit2 if \$t4 \$t3 move \$a0, \$s2 # 1st param of swap is v (old \$a0) move \$a1, \$s1 # 2nd param of swap is j jal swap # call swap procedure addi \$s1, \$s1, 1 # j = 1 j for2tst # jump to test of inner loop exit2: addi \$s0, \$s0, 1 # i += 1 j for1tst # jump to test of outer loop Move params Outer loop Inner loop Pass params & call Inner loop Outer loop Chapter 2 Instructions: Language of the Computer 35

36 The Full Procedure sort: addi \$sp,\$sp, 20 # make room on stack for 5 registers sw \$ra, 16(\$sp) # save \$ra on stack sw \$s3,12(\$sp) # save \$s3 on stack sw \$s2, 8(\$sp) # save \$s2 on stack sw \$s1, 4(\$sp) # save \$s1 on stack sw \$s0, 0(\$sp) # save \$s0 on stack # procedure body exit1: lw \$s0, 0(\$sp) # restore \$s0 from stack lw \$s1, 4(\$sp) # restore \$s1 from stack lw \$s2, 8(\$sp) # restore \$s2 from stack lw \$s3,12(\$sp) # restore \$s3 from stack lw \$ra,16(\$sp) # restore \$ra from stack addi \$sp,\$sp, 20 # restore stack pointer jr \$ra # return to calling routine Chapter 2 Instructions: Language of the Computer 36

37 Effect of Compiler Optimization Compiled with gcc for Pentium 4 under Linux 3 Relative Performance Instruction count none O1 O2 O3 0 none O1 O2 O Clock Cycles none O1 O2 O CPI none O1 O2 O3 Chapter 2 Instructions: Language of the Computer 37

38 Effect of Language and Algorithm 3 Bubblesort Relative Performance C/none C/O1 C/O2 C/O3 Java/int Java/JIT 2.5 Quicksort Relative Performance C/none C/O1 C/O2 C/O3 Java/int Java/JIT 3000 Quicksort vs. Bubblesort Speedup C/none C/O1 C/O2 C/O3 Java/int Java/JIT Chapter 2 Instructions: Language of the Computer 38

39 Lessons Learnt Instruction count and CPI are not good performance indicators in isolation Compiler optimizations are sensitive to the algorithm Java/JIT compiled code is significantly faster than JVM interpreted Comparable to optimized C in some cases Nothing can fix a dumb algorithm! Chapter 2 Instructions: Language of the Computer 39

40 ARM & MIPS Similarities ARM: the most popular embedded core Similar basic set of instructions to MIPS ARM MIPS Date announced Instruction size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data alignment Aligned Aligned Data addressing modes 9 3 Registers bit bit Input/output Memory mapped Memory mapped 2.16 Real Stuff: ARM Instructions Chapter 2 Instructions: Language of the Computer 40

41 Instruction Encoding Chapter 2 Instructions: Language of the Computer 41

42 The Intel x86 ISA Evolution with backward compatibility 8080 (1974): 8-bit microprocessor Accumulator, plus 3 index-register pairs 8086 (1978): 16-bit extension to 8080 Complex instruction set (CISC) 8087 (1980): floating-point coprocessor Adds FP instructions and register stack (1982): 24-bit addresses, MMU Segmented memory mapping and protection (1985): 32-bit extension (now IA-32) Additional addressing modes and operations Paged memory mapping as well as segments 2.17 Real Stuff: x86 Instructions Chapter 2 Instructions: Language of the Computer 42

43 The Intel x86 ISA Further evolution i486 (1989): pipelined, on-chip caches and FPU Compatible competitors: AMD, Cyrix, Pentium (1993): superscalar, 64-bit datapath Later versions added MMX (Multi-Media extension) instructions The infamous FDIV bug Pentium Pro (1995), Pentium II (1997) New microarchitecture (see Colwell, The Pentium Chronicles) Pentium III (1999) Added SSE (Streaming SIMD Extensions) and associated registers Pentium 4 (2001) New microarchitecture Added SSE2 instructions Chapter 2 Instructions: Language of the Computer 43

44 The Intel x86 ISA And further AMD64 (2003): extended architecture to 64 bits EM64T Extended Memory 64 Technology (2004) AMD64 adopted by Intel (with refinements) Added SSE3 instructions Intel Core (2006) Added SSE4 instructions, virtual machine support AMD64 (announced 2007): SSE5 instructions Intel declined to follow, instead Advanced Vector Extension (announced 2008) Longer SSE registers, more instructions If Intel didn t extend with compatibility, its competitors would! Technical elegance market success Chapter 2 Instructions: Language of the Computer 44

45 Basic x86 Registers Chapter 2 Instructions: Language of the Computer 45

46 Basic x86 Addressing Modes Two operands per instruction Source/dest operand Register Register Register Memory Memory Second source operand Register Immediate Memory Register Immediate Memory addressing modes Address in register Address = R base + displacement Address = R base + 2 scale R index (scale = 0, 1, 2, or 3) Address = R base + 2 scale R index + displacement Chapter 2 Instructions: Language of the Computer 46

47 x86 Instruction Encoding Variable length encoding Postfix bytes specify addressing mode Prefix bytes modify operation Operand length, repetition, locking, Chapter 2 Instructions: Language of the Computer 47

48 Implementing IA-32 Complex instruction set makes implementation difficult Hardware translates instructions to simpler microoperations Simple instructions: 1 1 Complex instructions: 1 many Microengine similar to RISC Market share makes this economically viable Comparable performance to RISC Compilers avoid complex instructions Chapter 2 Instructions: Language of the Computer 48

49 ARM v8 Instructions In moving to 64-bit, ARM did a complete overhaul ARM v8 resembles MIPS Changes from v7: No conditional execution field Immediate field is 12-bit constant Dropped load/store multiple PC is no longer a GPR GPR set expanded to 32 Addressing modes work for all word sizes Divide instruction Branch if equal/branch if not equal instructions 2.18 Real Stuff: ARM v8 (64-bit) Instructions Chapter 2 Instructions: Language of the Computer 49

50 Fallacies Powerful instruction higher performance Fewer instructions required But complex instructions are hard to implement May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code more errors and less productivity 2.19 Fallacies and Pitfalls Chapter 2 Instructions: Language of the Computer 50

51 Fallacies Backward compatibility instruction set doesn t change But they do accrete more instructions x86 instruction set Chapter 2 Instructions: Language of the Computer 51

52 Pitfalls Sequential words are not at sequential addresses Increment by 4, not by 1! Keeping a pointer to an automatic variable after procedure returns e.g., passing pointer back via an argument Pointer becomes invalid when stack popped Chapter 2 Instructions: Language of the Computer 52

53 Concluding Remarks Design principles 1. Simplicity favors regularity 2. Smaller is faster 3. Make the common case fast 4. Good design demands good compromises Layers of software/hardware Compiler, assembler, hardware MIPS: typical of RISC ISAs c.f. x Concluding Remarks Chapter 2 Instructions: Language of the Computer 53

54 Concluding Remarks Measure MIPS instruction executions in benchmark programs Consider making the common case fast Consider compromises Instruction class MIPS examples SPEC2006 Int SPEC2006 FP Arithmetic add, sub, addi 16% 48% Data transfer Logical Cond. Branch lw, sw, lb, lbu, lh, lhu, sb, lui and, or, nor, andi, ori, sll, srl beq, bne, slt, slti, sltiu 35% 36% 12% 4% 34% 8% Jump j, jr, jal 2% 0% Chapter 2 Instructions: Language of the Computer 54

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