Model Answer of System Software B. Tech. (4 th Semester Examination) Paper Code: AR Branch: Information Technology

Size: px
Start display at page:

Download "Model Answer of System Software B. Tech. (4 th Semester Examination) Paper Code: AR Branch: Information Technology"

Transcription

1 Model Answer of System Software B. Tech. (4 th Semester Examination) Paper Code: AR-9083 Branch: Information Technology Time Allowed: 3hours Maximum Marks: 100 Part-A (All questions are compulsory) Objective Type Questions (1*10=20Marks) Q.1. is device where information is stored. (a)data (b) Program (c) memory (d) File. Memory Q.2. is a hardware memory device which denotes the location of current instruction being executed (a) Instruction Counter (b) counter (c) templates (d) none of these. Instruction Counter Q.3. Which of the following loader is executed when a system is first turned on or restarted. (a) Boot loader (b) Compile and Go loader (c) Bootstrap loader (d) Relating loader Bootstrap loader Q.4. Nested Macro calls are expanded using the

2 (a) FIFO rule (First in first out) (b) LIFO (Last in First out) (c) FILO rule (First in last out) (d) None of these Q.5.In this operant form AREA +5(4) here 5 is the. (a) Pointer (b) Displacement (c) coding (d) none of these. Displacement Q.6.The primary function performed by the analysis phase is the building of the. (a) symbol Table (b) hashing (c) Localization (d) none of these. Symbol Table Q.7. expansion implies generation of instruction tailored to the requirements of a specific usage. (a) Semantic (b) next expansion (c) last expansion (d) none of these. Semantic Q.8.A model statement in a macro may constitute a call on another macro, such calls are known as calls. (a) Generated (b) nested (c) first (d) none of these. Nested Q.9. address assigned by the loader (a) load time (b) translate time (c) linked time (d) none of these. Load time. Q.10.Load origin assigned by while loading the program for execution.

3 (a) Linker, (b) programmer (c) Loader (d) none of these. Loader Short Answer Type Questions (2*5=10Marks) Q.1.What is memory? Fig.1. Memory hierarchy The smallest unit of memory is the "bit". A bit can be in one of two states on vs. off, or alternately, 1 vs. 0. Technically any object that can have two distinct states can remember one bit of information. This has been done with magnets, gear wheels, and tinker toys, but almost all computers use little transistor circuits called "flip-flops" to store bits. The flip-flop circuit has the property that it can be set to be in one of two states, and will stay in that state and can be read until it is reset. Q.2.Define Process?

4 Fig.2.Process in CPU. A process is an instance of a program running in a computer. It is close in meaning to task,. A process is started when a program is initiated (either by a user entering a shell command or by another program). Like a task, a process is a running program with which a particular set of data is associated so that the process can be kept track of. A process can initiate a sub process, which is a called a child process (and the initiating process is sometimes referred to as its parent). A child process is a replica of the parent process and shares some of its resources, but cannot exist if the parent is terminated. Q.3.Define Compiler?

5 Fig.3 A compiler is a program that translates human readable source code into computer executable machine code. To do this successfully the human readable code must comply with the syntax rules of whichever programming language it is written in. The compiler is only a program and cannot fix your programs for you. If you make a mistake, you have to correct the syntax or it won't compile. Q.4. what is interrupts in C? Fig.4 An interrupt is a hardware mechanism that enables an external device, typically I/O devices, to send a signal to the CPU. An interrupt signal requests the CPU to interrupt its current activities

6 and attend to the interrupting device s needs. A CPU will check interrupts only after it has completed the processing of one instruction and before it fetches a subsequent one Q.5.Define intermediate code? Fig.5 An intermediate code is basically governed during the process of conversion from analysis phase to synthesis phase of assembler. And the intermediate code is between translator and code generator. Section B Each Question carries 8 marks. (Long answer type questions 8*5 =40 Marks) Note: Attempt any one questions out of two questions from each unit. Unit 1 Q.1. Explain in detail the following terms (a) Memory Address Registers (b)memory Buffer Registers

7 Fig.6 Memory address Register (MAR): MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. Memory Buffer Registers (MBR): A Memory Buffer Register (MBR) is the register in a computer's processor, or central processing unit, CPU, that stores the data being transferred to and from the immediate access store. It acts as a buffer allowing the processor and memory units to act independently without being affected by minor differences in operation. A data item will be copied to the MBR ready for use at the next clock cycle, when it can be either used by the processor or stored in main memory. Q.2. Explain pointer in detail, its various declaration methods? Pointer is a variable that stores value of address of a variable. Since pointer itself is a variable, it is allocated a memory location. Pointer to pointer is a pointer which points to the address of a pointer. In other words a pointer to pointer has the address of address of a variable.

8 Consider the declaration, Int i = 3 ; This declaration tells the C compiler to: (a) Reserve space in memory to hold the integer value. (b) Associate the name i with this memory location. (c) Store the value 3 at this location. Example. Meaning of following simple pointer declaration int a=5; int * ptr; ptr=&a; Explanation: About variable a: 1. Name of variable : a 2. Value of variable which it keeps: 5 3. Address where it has stored in memory : 1025 (assume) About variable ptr: 4. Name of variable : ptr 5. Value of variable which it keeps: Address where it has stored in memory : 5000 (assume) Unit 2 Q.1.Explain the types of interrupt in detail?

9 Fig.7 Interrupts alter a program s flow of control its behavior is similar to a procedure call, interrupts causes transfer of control to an interrupt service routine (ISR), it is also called a handler. Interrupts provide an efficient way to handle unanticipated events. Various Ways of Interacting with I/O Device Fig.8 Types of Interrupt A. Software Interrupt B. Hardware Interrupt

10 C. Exceptions Interrupt A. Software Interrupt: Software interrupt is basically Initiated by executing an interrupt instruction int interrupt-type,interrupt-type is an integer in the range 0 to255. Each interrupt type can be parameterized to provide several services. For example, DOS interrupt service int 21H provides more than 80 different services; AH register is used to identify the required service under int 21H. As with DOS functions, AH is used to identify the required service. B. Hardware Interrupt: Fig. 9 Hardware interrupts are of hardware origin and asynchronous in nature. Typically it is caused by applying an electrical signal to the Processor chip Hardware interrupts can be Mask able and Non-mask able. C. Exceptions Interrupt: Exceptions Interrupt are divided in to three parts, depends on the way they are reported. Faults and traps are reported at instruction boundaries (a) Faults: It is in the instruction boundaries during which the execution was detected, it restart the instruction, it also detected during div/idiv instruction. (b)traps: Instruction boundary immediately after the instruction during, which the exception was detected. It is not allowing any instruction to restart.

11 (c) Aborts: Abort interrupt sever errors such as hardware errors, and inconsistent values in system tables. Q.2.Explain in detail the hardware interrupts? Fig. 10 Hardware interrupts are of hardware origin and asynchronous in nature. Typically it is caused by applying an electrical signal to the Processor chip Hardware interrupts can be Mask able and Non-mask able.

12 Non-maskable interrupt is triggered by applying an electrical signal to the MNI pin of Pentium and Processor always responds to this signal it cannot be disabled under program control. Maskable interrupt is triggered by applying an electrical signal to the INTR (INTerrupt Request) pin of Pentium. Pentium recognizes this interrupt only if IF (interrupt enable flag) is set. Interrupts can be masked or disabled by clearing IF. For hardware interrupts, CPU initiates an interrupt known as acknowledge sequence. CPU sends out interrupt acknowledge (INTA) signal in response, interrupting device places interrupt type number on the data bus. CPU uses this number to invoke the ISR that should service the device (as in software interrupts) Unit 3 Q.1.Explain in detail the advantages of Assembly Languages?

13 Fig.11 The Primary advantages of assembly language programming vis -a - vis machine language programming arise from the use symbolic operant specification.assembly language holds an

14 edge over HLL(High level language ) programming. Assembly language programming uses the special instruction support by the CPU. It processes the source statements in a text file to produce a relocate able object file. It produces a source listing (if requested) and provides you with control over this listing. It allows you to divide your code into sections and maintain a section program counter (SPC) for each Section of object code. It defines and references global symbols and appends a cross-reference listing to the source listing (if requested) It also allows conditional assembly It supports macros, allowing you to define macros inline or in a library. Q.2.Describe the specification of Assembler? Ans. Fig.12

15 The basic specification of Assembler is as followed in four steps. a. Identify the information necessary to perform a task. b. Design a suitable data structure to record the information c. Determine the processing necessary to obtain and maintain the information d. Determine the necessary processing to perform the task. The data structure used during the synthesis phase are symbol table and mnemonic table, and the primery function of analysis phase is the building of symbol table. Analysis Phase. a.isolate the label, mnemonic opcode operand fields of a statement. b.if a label is present, enter the pair in a new enter of a symbol table c.check the validity of the mnemonic opcode d. Perform LC processing Synthesis Phase a. Obtain the machine opcode corresponding to the mnemonic from the mnemonic table. b. obtain the address from the symbol table c. synthesize the machine instruction Unit 4 Q.1.Explain in detail the semantic expansion in macro expansion? Semantic expansion implies generation of instruction tailored to the requirement of a specific usage.

16 Semantic expansion is characterized by the fact that different uses of a macro can lead codes which differ in number, sequence and opcode instruction. Example. The following sequence of instruction is used to increment the value in memory word by a constant. a. Move the value from the memory word in to a Machine register. b. Increment the value in the machine register. c. Move the new value in to the memory word Q.2.Explain in detail the concept of macro calls? A macro is called by writing a macro name in the mnemonic field of an assembly statement. the macro call has the syntax <macro name>[<actual parameter spec> [,..]] Where actual parameter typically resembles an opcode specification in an assembly language statement. Unit 5 Q.1.Explain the concept of relocation in detail?

17 Fig.13 Program relocation is the process of modifying the address used in the address sensitive instruction of a program such that the program can execute correctly from the designated are of the memory Relocation is basically consists of a. An address sensitive instruction: A set of absolute address, instruction or data. b. An address constant: A data word which contain the address of sensitive instruction Relocation is the process of shifting the address of memory from static to dynamic binding of memory address of an instruction. Q.2. Explain the concept of Linking in detail?

18 Fig.14 Linking is basically consist of a. Public definition : a symbol pub_symb defined in a program unit which may be reference in other program units. b. External reference: a reference to symbol ext_symbol which is not defined in the program unit containing the reference.

19 Linking is the process of binding an external reference to the correct link time address.external reference is said to be unresolved until linking is performed for it. It is said to be resolved when its linking is completed. Finely linking load the executable file in the memory for the further execution of program.

Interrupt is a process where an external device can get the attention of the microprocessor. Interrupts can be classified into two types:

Interrupt is a process where an external device can get the attention of the microprocessor. Interrupts can be classified into two types: 8085 INTERRUPTS 1 INTERRUPTS Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device The process is asynchronous. Classification

More information

Interrupts. by Rahul Patel, Assistant Professor, EC Dept., Sankalchand Patel College of Engg.,Visnagar

Interrupts. by Rahul Patel, Assistant Professor, EC Dept., Sankalchand Patel College of Engg.,Visnagar Chapter 12 Interrupts by Rahul Patel, Assistant Professor, EC Dept., Sankalchand Patel College of Engg.,Visnagar Microprocessor & Interfacing (140701) Rahul Patel 1 Points to be Discussed 8085 Interrupts

More information

8085 Interrupts. Lecturer, CSE, AUST

8085 Interrupts. Lecturer, CSE, AUST 8085 Interrupts CSE 307 - Microprocessors Mohd. Moinul Hoque, 1 Interrupts Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device

More information

Sunday, April 25, 2010

Sunday, April 25, 2010 Sunday, April 25, 2010 BSNL TTA EXAM MICRO PROCESSER BSNL TTA EXAM MICRO PROCESSER 1. A 32-bit processor has (a) 32 registers (b) 32 I/O devices (c) 32 Mb of RAM (d) a 32-bit bus or 32-bit registers 2.

More information

AS-2883 B.Sc.(Hon s)(fifth Semester) Examination,2013 Computer Science (PCSC-503) (System Software) [Time Allowed: Three Hours] [Maximum Marks : 30]

AS-2883 B.Sc.(Hon s)(fifth Semester) Examination,2013 Computer Science (PCSC-503) (System Software) [Time Allowed: Three Hours] [Maximum Marks : 30] AS-2883 B.Sc.(Hon s)(fifth Semester) Examination,2013 Computer Science (PCSC-503) (System Software) [Time Allowed: Three Hours] [Maximum Marks : 30] Note: Question Number 1 is compulsory. Marks : 10X1

More information

8086 Interrupts and Interrupt Responses:

8086 Interrupts and Interrupt Responses: UNIT-III PART -A INTERRUPTS AND PROGRAMMABLE INTERRUPT CONTROLLERS Contents at a glance: 8086 Interrupts and Interrupt Responses Introduction to DOS and BIOS interrupts 8259A Priority Interrupt Controller

More information

Microprocessor Architecture

Microprocessor Architecture Microprocessor - 8085 Architecture 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration

More information

General purpose registers These are memory units within the CPU designed to hold temporary data.

General purpose registers These are memory units within the CPU designed to hold temporary data. Von Neumann Architecture Single processor is used Each instruction in a program follows a linear sequence of fetch decode execute cycle Program and data are held in same main memory Stored program Concept

More information

What Are The Main Differences Between Program Counter Pc And Instruction Register Ir

What Are The Main Differences Between Program Counter Pc And Instruction Register Ir What Are The Main Differences Between Program Counter Pc And Instruction Register Ir and register-based instructions - Anatomy on a CPU - Program Counter (PC): holds memory address of next instruction

More information

PSD1C SYSTEM SOFTWAE UNIT: I - V PSD1C SYSTEM SOFTWARE

PSD1C SYSTEM SOFTWAE UNIT: I - V PSD1C SYSTEM SOFTWARE PSD1C SYSTEM SOFTWAE UNIT: I - V 1 Syllabus Unit-I Language Processors Types of Language Processors Language Processing Activities Fundamentals of Language Processing Language Specification Data Structures

More information

Types of Interrupts:

Types of Interrupts: Interrupt structure Introduction Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task or work. Mainly in the microprocessor based system

More information

EEL 4744C: Microprocessor Applications. Lecture 7. Part 1. Interrupt. Dr. Tao Li 1

EEL 4744C: Microprocessor Applications. Lecture 7. Part 1. Interrupt. Dr. Tao Li 1 EEL 4744C: Microprocessor Applications Lecture 7 Part 1 Interrupt Dr. Tao Li 1 M&M: Chapter 8 Or Reading Assignment Software and Hardware Engineering (new version): Chapter 12 Dr. Tao Li 2 Interrupt An

More information

Reading Assignment. Interrupt. Interrupt. Interrupt. EEL 4744C: Microprocessor Applications. Lecture 7. Part 1

Reading Assignment. Interrupt. Interrupt. Interrupt. EEL 4744C: Microprocessor Applications. Lecture 7. Part 1 Reading Assignment EEL 4744C: Microprocessor Applications Lecture 7 M&M: Chapter 8 Or Software and Hardware Engineering (new version): Chapter 12 Part 1 Interrupt Dr. Tao Li 1 Dr. Tao Li 2 Interrupt An

More information

Control Unit: The control unit provides the necessary timing and control Microprocessor resembles a CPU exactly.

Control Unit: The control unit provides the necessary timing and control Microprocessor resembles a CPU exactly. Unit I 8085 and 8086 PROCESSOR Introduction to microprocessor A microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale

More information

EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers UNIT-I

EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers UNIT-I EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers 1. Define microprocessors? UNIT-I A semiconductor device(integrated circuit) manufactured by using the LSI technique. It includes

More information

UNIT I. Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK-4. 1

UNIT I. Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK-4. 1 Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK-4. 1 UNIT I Introduction: Components of System Software: Text editors, Loaders, Assemblers, Macro processors, Compilers, Debuggers. Machine Structure,

More information

CPU Structure and Function

CPU Structure and Function Computer Architecture Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com http://www.yildiz.edu.tr/~naydin CPU Structure and Function 1 2 CPU Structure Registers

More information

Chapter 1: Basics of Microprocessor [08 M]

Chapter 1: Basics of Microprocessor [08 M] Microprocessor: Chapter 1: Basics of Microprocessor [08 M] It is a semiconductor device consisting of electronic logic circuits manufactured by using either a Large scale (LSI) or Very Large Scale (VLSI)

More information

SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE EC6504 MICROPROCESSOR AND MICROCONTROLLER (REGULATION 2013)

SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE EC6504 MICROPROCESSOR AND MICROCONTROLLER (REGULATION 2013) SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE EC6504 MICROPROCESSOR AND MICROCONTROLLER (REGULATION 2013) UNIT I THE 8086 MICROPROCESSOR PART A (2 MARKS) 1. What are the functional

More information

Basics of Microprocessor

Basics of Microprocessor Unit 1 Basics of Microprocessor 1. Microprocessor Microprocessor is a multipurpose programmable integrated device that has computing and decision making capability. This semiconductor IC is manufactured

More information

Interrupts. Chapter 20 S. Dandamudi. Outline. Exceptions

Interrupts. Chapter 20 S. Dandamudi. Outline. Exceptions Interrupts Chapter 20 S. Dandamudi Outline What are interrupts? Types of interrupts Software interrupts Hardware interrupts Exceptions Interrupt processing Protected mode Real mode Software interrupts

More information

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition CPU Structure and Function Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition CPU must: CPU Function Fetch instructions Interpret/decode instructions Fetch data Process data

More information

VARDHAMAN COLLEGE OF ENGINEERING (AUTONOMOUS) Shamshabad, Hyderabad

VARDHAMAN COLLEGE OF ENGINEERING (AUTONOMOUS) Shamshabad, Hyderabad Introduction to MS-DOS Debugger DEBUG In this laboratory, we will use DEBUG program and learn how to: 1. Examine and modify the contents of the 8086 s internal registers, and dedicated parts of the memory

More information

The Purpose of Interrupt

The Purpose of Interrupt Interrupts 3 Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is a hardware-initiated

More information

In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.

In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag. What is a Microprocessor? Microprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions. Most Micro Processor are single- chip devices.

More information

These three counters can be programmed for either binary or BCD count.

These three counters can be programmed for either binary or BCD count. S5 KTU 1 PROGRAMMABLE TIMER 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers.

More information

CPU Structure and Function

CPU Structure and Function CPU Structure and Function Chapter 12 Lesson 17 Slide 1/36 Processor Organization CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Lesson 17 Slide 2/36 CPU With Systems

More information

Module 5 - CPU Design

Module 5 - CPU Design Module 5 - CPU Design Lecture 1 - Introduction to CPU The operation or task that must perform by CPU is: Fetch Instruction: The CPU reads an instruction from memory. Interpret Instruction: The instruction

More information

1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085.

1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085. (1) Draw and explain the internal architecture of 8085. The architecture of 8085 Microprocessor is shown in figure given below. The internal architecture of 8085 includes following section ALU-Arithmetic

More information

MACHINE CONTROL INSTRUCTIONS: 1. EI

MACHINE CONTROL INSTRUCTIONS: 1. EI Lecture-33 MACHINE CONTROL INSTRUCTIONS: 1. EI (Enable interrupts): The interrupt system is disabled just after RESET operation. There is an internal INTE F/F (Interrupt enable flipflop) which is reset

More information

William Stallings Computer Organization and Architecture. Chapter 11 CPU Structure and Function

William Stallings Computer Organization and Architecture. Chapter 11 CPU Structure and Function William Stallings Computer Organization and Architecture Chapter 11 CPU Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Registers

More information

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5.

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5. DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6502- MICROPROCESSORS AND MICROCONTROLLERS UNIT I: 8085 PROCESSOR PART A 1. What is the need for ALE signal in

More information

Digital System Design Using Verilog. - Processing Unit Design

Digital System Design Using Verilog. - Processing Unit Design Digital System Design Using Verilog - Processing Unit Design 1.1 CPU BASICS A typical CPU has three major components: (1) Register set, (2) Arithmetic logic unit (ALU), and (3) Control unit (CU) The register

More information

1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE:

1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE: 1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE: A microprocessor is a programmable electronics chip that has computing and decision making capabilities similar to central processing unit

More information

27 December 2016 Pramod Ghimire. Slide 1 of 16

27 December 2016 Pramod Ghimire. Slide 1 of 16 8259-Programmable Interrupt Controller (8259-PIC) Slide 1 of 16 Programmable Interface Device A Programmable interface device is designed to perform various input/output functions. Such a device can be

More information

B. the address of the data is supplied by the users C. there is no need for an address i.e. the data is used as an address

B. the address of the data is supplied by the users C. there is no need for an address i.e. the data is used as an address 1. The part of machine level instruction, which tells the central processor what has to be done, is A. Operation code B. Address C. Locator D. Flip-Flop 2. Which of the following refers to the associative

More information

MLR Institute of Technology

MLR Institute of Technology MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Phone Nos: 08418 204066 / 204088, Fax : 08418 204088 ELECTRONICS AND COMMUNICATION ENGINEERING OBJECTIVE TYPE

More information

1. Internal Architecture of 8085 Microprocessor

1. Internal Architecture of 8085 Microprocessor 1. Internal Architecture of 8085 Microprocessor Control Unit Generates signals within up to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the

More information

8/26/2010. Introduction to 8085 BLOCK DIAGRAM OF INTEL Introduction to Introduction to Three Units of 8085

8/26/2010. Introduction to 8085 BLOCK DIAGRAM OF INTEL Introduction to Introduction to Three Units of 8085 BLOCK DIAGRAM OF INTEL 8085 GURSHARAN SINGH TATLA Introduction to 8085 It was introduced in 1977. It is 8-bit microprocessor. Its actual name is 8085 A. It is single NMOS device. It contains 6200 transistors

More information

MICROPROGRAMMED CONTROL

MICROPROGRAMMED CONTROL MICROPROGRAMMED CONTROL Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed

More information

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015 Advanced Parallel Architecture Lesson 3 Annalisa Massini - 2014/2015 Von Neumann Architecture 2 Summary of the traditional computer architecture: Von Neumann architecture http://williamstallings.com/coa/coa7e.html

More information

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 11 Instruction Sets: Addressing Modes and Formats

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 11 Instruction Sets: Addressing Modes and Formats William Stallings Computer Organization and Architecture 8 th Edition Chapter 11 Instruction Sets: Addressing Modes and Formats Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement

More information

12-Dec-11. Gursharan Singh Maninder Kaur. Introduction to 8085 BLOCK DIAGRAM OF INTEL Introduction to Introduction to 8085

12-Dec-11. Gursharan Singh Maninder Kaur. Introduction to 8085 BLOCK DIAGRAM OF INTEL Introduction to Introduction to 8085 mailme@gursharansingh.in BLOCK DIAGRAM OF INTEL 8085 mailme@maninderkaur.in Introduction to 8085 It was introduced in 1977. It is 8-bit microprocessor. Its actual name is 8085 A. It is single NMOS device.

More information

Computer Architecture and Organization. Instruction Sets: Addressing Modes and Formats

Computer Architecture and Organization. Instruction Sets: Addressing Modes and Formats Computer Architecture and Organization Instruction Sets: Addressing Modes and Formats Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack Immediate Addressing

More information

Digital IP Cell 8-bit Microcontroller PE80

Digital IP Cell 8-bit Microcontroller PE80 1. Description The is a Z80 compliant processor soft-macro - IP block that can be implemented in digital or mixed signal ASIC designs. The Z80 and its derivatives and clones make up one of the most commonly

More information

Outcomes. Lecture 13 - Introduction to the Central Processing Unit (CPU) Central Processing UNIT (CPU) or Processor

Outcomes. Lecture 13 - Introduction to the Central Processing Unit (CPU) Central Processing UNIT (CPU) or Processor Lecture 13 - Introduction to the Central Processing Unit (CPU) Outcomes What is a CPU? How are instructions prepared by the CPU before execution? What registers and operations are involved in this preparation

More information

BASIC INTERRUPT PROCESSING

BASIC INTERRUPT PROCESSING Interrupts BASIC INTERRUPT PROCESSING This section discusses the function of an interrupt in a microprocessor-based system. Structure and features of interrupts available to Intel microprocessors. The

More information

Author : Dalbir Singh, Computer Science Deptt. CPU Structure and Functions. 1. Processor Organization

Author : Dalbir Singh, Computer Science Deptt. CPU Structure and Functions. 1. Processor Organization Author : Dalbir Singh, Computer Science Deptt. CPU Structure and Functions 1. Processor Organization To understand the organization of the CPU, let us consider the requirements placed on the CPU, the things

More information

UNIT I - INTRODUCTION

UNIT I - INTRODUCTION UNIT I - INTRODUCTION 1. Define system software. It consists of variety of programs that supports the operation of the computer. This software makes it possible for the user to focus on the other problems

More information

Basic Processing Unit: Some Fundamental Concepts, Execution of a. Complete Instruction, Multiple Bus Organization, Hard-wired Control,

Basic Processing Unit: Some Fundamental Concepts, Execution of a. Complete Instruction, Multiple Bus Organization, Hard-wired Control, UNIT - 7 Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction, Multiple Bus Organization, Hard-wired Control, Microprogrammed Control Page 178 UNIT - 7 BASIC PROCESSING

More information

Chapter 1 Microprocessor architecture ECE 3120 Dr. Mohamed Mahmoud http://iweb.tntech.edu/mmahmoud/ mmahmoud@tntech.edu Outline 1.1 Computer hardware organization 1.1.1 Number System 1.1.2 Computer hardware

More information

MICROPROCESSOR AND MICROCONTROLLER BASED SYSTEMS

MICROPROCESSOR AND MICROCONTROLLER BASED SYSTEMS MICROPROCESSOR AND MICROCONTROLLER BASED SYSTEMS UNIT I INTRODUCTION TO 8085 8085 Microprocessor - Architecture and its operation, Concept of instruction execution and timing diagrams, fundamentals of

More information

Compiler, Assembler, and Linker

Compiler, Assembler, and Linker Compiler, Assembler, and Linker Minsoo Ryu Department of Computer Science and Engineering Hanyang University msryu@hanyang.ac.kr What is a Compilation? Preprocessor Compiler Assembler Linker Loader Contents

More information

Blog -

Blog - . Instruction Codes Every different processor type has its own design (different registers, buses, microoperations, machine instructions, etc) Modern processor is a very complex device It contains Many

More information

Chapter 7 Central Processor Unit (S08CPUV2)

Chapter 7 Central Processor Unit (S08CPUV2) Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more

More information

Architecture of 8085 microprocessor

Architecture of 8085 microprocessor Architecture of 8085 microprocessor 8085 consists of various units and each unit performs its own functions. The various units of a microprocessor are listed below Accumulator Arithmetic and logic Unit

More information

UNIT-II. Part-2: CENTRAL PROCESSING UNIT

UNIT-II. Part-2: CENTRAL PROCESSING UNIT Page1 UNIT-II Part-2: CENTRAL PROCESSING UNIT Stack Organization Instruction Formats Addressing Modes Data Transfer And Manipulation Program Control Reduced Instruction Set Computer (RISC) Introduction:

More information

CHAPTER 5 : Introduction to Intel 8085 Microprocessor Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY

CHAPTER 5 : Introduction to Intel 8085 Microprocessor Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY CHAPTER 5 : Introduction to Intel 8085 Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY The 8085A(commonly known as the 8085) : Was first introduced in March 1976 is an 8-bit microprocessor with 16-bit address

More information

Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit

Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit Lecture1: introduction Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit 1 1. History overview Computer systems have conventionally

More information

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2 Class Notes CS400 Part VI Dr.C.N.Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2 C. N. Zhang, CS400 83 VI. CENTRAL PROCESSING UNIT 1 Set 1.1 Addressing Modes and Formats

More information

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system.

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. CPU ARCHITECTURE QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. ANSWER 1 Data Bus Width the width of the data bus determines the number

More information

Chapter 12. CPU Structure and Function. Yonsei University

Chapter 12. CPU Structure and Function. Yonsei University Chapter 12 CPU Structure and Function Contents Processor organization Register organization Instruction cycle Instruction pipelining The Pentium processor The PowerPC processor 12-2 CPU Structures Processor

More information

The functional block diagram of 8085A is shown in fig.4.1.

The functional block diagram of 8085A is shown in fig.4.1. Lecture-13 Internal Architecture of Intel 05A The functional block diagram of 05A is shown in fig.4.1. INTA INTR RST7.5 RST5.5 RST6.5 TRAP SOD SID INTERRUPT SERIAL I/O (Internal Bus) FR(S) IR() B() C()

More information

ADVANCED COMPUTER ARCHITECTURE TWO MARKS WITH ANSWERS

ADVANCED COMPUTER ARCHITECTURE TWO MARKS WITH ANSWERS ADVANCED COMPUTER ARCHITECTURE TWO MARKS WITH ANSWERS 1.Define Computer Architecture Computer Architecture Is Defined As The Functional Operation Of The Individual H/W Unit In A Computer System And The

More information

Introduction to Microprocessor

Introduction to Microprocessor Introduction to Microprocessor The microprocessor is a general purpose programmable logic device. It is the brain of the computer and it performs all the computational tasks, calculations data processing

More information

There are different characteristics for exceptions. They are as follows:

There are different characteristics for exceptions. They are as follows: e-pg PATHSHALA- Computer Science Computer Architecture Module 15 Exception handling and floating point pipelines The objectives of this module are to discuss about exceptions and look at how the MIPS architecture

More information

What Operating Systems Do An operating system is a program hardware that manages the computer provides a basis for application programs acts as an int

What Operating Systems Do An operating system is a program hardware that manages the computer provides a basis for application programs acts as an int Operating Systems Lecture 1 Introduction Agenda: What Operating Systems Do Computer System Components How to view the Operating System Computer-System Operation Interrupt Operation I/O Structure DMA Structure

More information

COSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1

COSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 COSC 243 Computer Architecture 1 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 Overview Last Lecture Flip flops This Lecture Computers Next Lecture Instruction sets and addressing

More information

Chapter 3 : Control Unit

Chapter 3 : Control Unit 3.1 Control Memory Chapter 3 Control Unit The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional

More information

A First Look at Microprocessors

A First Look at Microprocessors A First Look at Microprocessors using the The General Prototype Computer (GPC) model Part 4 Ports CPU Ecosystem All CPUs need RAM, ROM, a clock source and reset circuit, and power. Power Supply 1 Vio Vcore

More information

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 12 Processor Structure and Function

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 12 Processor Structure and Function William Stallings Computer Organization and Architecture 8 th Edition Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data

More information

PESIT Bangalore South Campus

PESIT Bangalore South Campus Fourth Semester B.E. IA Test-1, 2015 USN 1 P E I S PESIT Bangalore South Campus (Hosur Road, 1KM before Electronic City, Bangalore-560 100) Department of Information Science & Engineering Section: 4 th

More information

COMPILER DESIGN. For COMPUTER SCIENCE

COMPILER DESIGN. For COMPUTER SCIENCE COMPILER DESIGN For COMPUTER SCIENCE . COMPILER DESIGN SYLLABUS Lexical analysis, parsing, syntax-directed translation. Runtime environments. Intermediate code generation. ANALYSIS OF GATE PAPERS Exam

More information

Major and Minor States

Major and Minor States Major and Minor States We now consider the micro operations and control signals associated with the execution of each instruction in the ISA. The execution of each instruction is divided into three phases.

More information

The Assembly Language Level. Chapter 7

The Assembly Language Level. Chapter 7 The Assembly Language Level Chapter 7 Definitions Translator Converts user program to another language Source language Language of original program Target language Language into which source code is converted

More information

7/19/2013. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to: Chapter Objectives 12 1 BASIC INTERRUPT PROCESSING

7/19/2013. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to: Chapter Objectives 12 1 BASIC INTERRUPT PROCESSING Chapter 12: Interrupts Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is

More information

Chapter 12: Interrupts

Chapter 12: Interrupts Chapter 12: Interrupts Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is

More information

4. (a) With a neat sketch explain 8237 DMA controller and its operation? (b) With the help of basic cell explain SRAM and DRAM?

4. (a) With a neat sketch explain 8237 DMA controller and its operation? (b) With the help of basic cell explain SRAM and DRAM? Code No: R05220504 Set No. 1 II B.Tech II Semester Regular Examinations, Apr/May 2008 MICROPROCESSORS AND INTERFACING ( Common to Computer Science & Engineering, Information Technology and Computer Science

More information

UNIT II SYSTEM BUS STRUCTURE 1. Differentiate between minimum and maximum mode 2. Give any four pin definitions for the minimum mode. 3. What are the pins that are used to indicate the type of transfer

More information

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics Chapter 4 Objectives Learn the components common to every modern computer system. Chapter 4 MARIE: An Introduction to a Simple Computer Be able to explain how each component contributes to program execution.

More information

4) In response to the the 8259A sets the highest priority ISR, bit and reset the corresponding IRR bit. The 8259A also places

4) In response to the the 8259A sets the highest priority ISR, bit and reset the corresponding IRR bit. The 8259A also places Lecture-52 Interrupt sequence: The powerful features of the 8259A in a system are its programmability and the interrupt routine address capability. It allows direct or indirect jumping to the specific

More information

UNIT- 5. Chapter 12 Processor Structure and Function

UNIT- 5. Chapter 12 Processor Structure and Function UNIT- 5 Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data CPU With Systems Bus CPU Internal Structure Registers

More information

There are four registers involved in the fetch cycle: MAR, MBR, PC, and IR.

There are four registers involved in the fetch cycle: MAR, MBR, PC, and IR. CS 320 Ch. 20 The Control Unit Instructions are broken down into fetch, indirect, execute, and interrupt cycles. Each of these cycles, in turn, can be broken down into microoperations where a microoperation

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com CHAPTER -2 2.1 Basic Assembler Functions: The basic assembler functions are: ASSEMBLERS-1 Translating mnemonic language code to its equivalent object code. Assigning machine addresses to symbolic labels.

More information

Fredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт.

Fredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт. SECOND шт. Assembly and С Programming forthefreescalehcs12 Microcontroller Fredrick M. Cady Department of Electrical and Computer Engineering Montana State University New York Oxford Oxford University

More information

B. V. Patel Institute of Business Management, Computer &Information Technology, UTU

B. V. Patel Institute of Business Management, Computer &Information Technology, UTU BCA-3 rd Semester 030010304-Fundamentals Of Operating Systems Unit: 1 Introduction Short Answer Questions : 1. State two ways of process communication. 2. State any two uses of operating system according

More information

This section covers the MIPS instruction set.

This section covers the MIPS instruction set. This section covers the MIPS instruction set. 1 + I am going to break down the instructions into two types. + a machine instruction which is directly defined in the MIPS architecture and has a one to one

More information

Lecture-15 W-Z: Increment-Decrement Address Latch:

Lecture-15 W-Z: Increment-Decrement Address Latch: Lecture-15 W-Z: (W) and (Z) are two 8-bit temporary registers not accessible to the user. They are exclusively used for the internal operation by the microprocessor. These registers are used either to

More information

Systems Programming and Computer Architecture ( ) Timothy Roscoe

Systems Programming and Computer Architecture ( ) Timothy Roscoe Systems Group Department of Computer Science ETH Zürich Systems Programming and Computer Architecture (252-0061-00) Timothy Roscoe Herbstsemester 2016 AS 2016 Exceptions 1 17: Exceptions Computer Architecture

More information

Question Bank Part-A UNIT I- THE 8086 MICROPROCESSOR 1. What is microprocessor? A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device that reads binary information

More information

Microprocessors & Interfacing

Microprocessors & Interfacing Lecture Overview Microprocessors & Interfacing Interrupts (I) Lecturer : Dr. Annie Guo Introduction to Interrupts Interrupt system specifications Multiple sources of interrupts Interrupt priorities Interrupts

More information

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013 CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013 TOPICS TODAY I/O Architectures Interrupts Exceptions FETCH EXECUTE CYCLE 1.7 The von Neumann Model This is a general

More information

Objectives. ICT106 Fundamentals of Computer Systems Topic 8. Procedures, Calling and Exit conventions, Run-time Stack Ref: Irvine, Ch 5 & 8

Objectives. ICT106 Fundamentals of Computer Systems Topic 8. Procedures, Calling and Exit conventions, Run-time Stack Ref: Irvine, Ch 5 & 8 Objectives ICT106 Fundamentals of Computer Systems Topic 8 Procedures, Calling and Exit conventions, Run-time Stack Ref: Irvine, Ch 5 & 8 To understand how HLL procedures/functions are actually implemented

More information

OPERATING SYSTEMS. Goals of the Course. This lecture will cover: This Lecture will also cover:

OPERATING SYSTEMS. Goals of the Course. This lecture will cover: This Lecture will also cover: OPERATING SYSTEMS This lecture will cover: Goals of the course Definitions of operating systems Operating system goals What is not an operating system Computer architecture O/S services This Lecture will

More information

PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru Department of Electronics and Communication Engineering

PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru Department of Electronics and Communication Engineering PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -560100 Department of Electronics and Communication Engineering Faculty: Richa Sharma Subject: Operating System SCHEME & SOLUTION

More information

COMPILER DESIGN LEXICAL ANALYSIS, PARSING

COMPILER DESIGN LEXICAL ANALYSIS, PARSING COMPILER DESIGN LEXICAL ANALYSIS, PARSING 1. Which of the following system program forgoes the production of object code to generate absolute machine code and load it into the Physical main storage location

More information

Instructions Involve a Segment Register (SR-field)

Instructions Involve a Segment Register (SR-field) BYTE 1 = 11000111 2 = C7 16 BYTE 2 = (MOD)000(R/M) = 100000112 = 83 16 BYTE 3 = 34 16 and BYTE 4 = 12 16 BYTE 5 = CD 16 and BYTE 6 = AB 16 The machine code for the instruction is: MOV [BP+DI+1234H], 0ABCDH

More information

Interrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1

Interrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1 Interrupts (I) Lecturer: Sri Notes by Annie Guo Week8 1 Lecture overview Introduction to Interrupts Interrupt system specifications Multiple Sources of Interrupts Interrupt Priorities Interrupts in AVR

More information

Compiler Design. Computer Science & Information Technology (CS) Rank under AIR 100

Compiler Design. Computer Science & Information Technology (CS) Rank under AIR 100 GATE- 2016-17 Postal Correspondence 1 Compiler Design Computer Science & Information Technology (CS) 20 Rank under AIR 100 Postal Correspondence Examination Oriented Theory, Practice Set Key concepts,

More information

QUESTION BANK. EE 6502 / Microprocessor and Microcontroller. Unit I Processor. PART-A (2-Marks)

QUESTION BANK. EE 6502 / Microprocessor and Microcontroller. Unit I Processor. PART-A (2-Marks) QUESTION BANK EE 6502 / Microprocessor and Microcontroller Unit I- 8085 Processor PART-A (2-Marks) YEAR/SEM : III/V 1. What is meant by Level triggered interrupt? Which are the interrupts in 8085 level

More information