McGILL UNIVERSITY Electrical and Computer Engineering Department MIDTERM EXAM

Size: px

Start display at page:

Download "McGILL UNIVERSITY Electrical and Computer Engineering Department MIDTERM EXAM"

Damian Kelly
5 years ago
Views:

1 McGILL UNIVERSITY Electrical and Computer Engineering Department ECSE-323 DIGITAL SYSTEM DESIGN MIDTERM EXAM Winter 2010 Question Maximum Points Points Attained Total 75 Please write down your name: Please write your student ID number: Instructions/Please read carefully! This is a closed book quiz. No books or notes are allowed. You may use a standard calculator. All work is to be done on the attached sheets and under no circumstance are booklets or loose sheets to be used. Write your name at the top of every sheet. Read the question carefully. If something appears ambiguous, write down your assumption. The points have been assigned according to the formula that 1 point = 1 exam minute, so please pace yourself accordingly. Page 1 of 17

2 Question 1: Boolean Logic Theory (15 marks) Consider the following Boolean function: f(b,d,f,g,e) = bdg+b dfg+b d g+bd eg. a) Find the minimal SoP form of function f using the Quine-McCluskey method. Clearly state which are the essential prime implicants and prime implicants. b) Perform the factorization of the minimized SoP from part b). Try to get as small a form as possible. c) Perform the decomposition of the minimized function from part b). Solution a) We need to express f in terms of minterms. f(b,d,f,g,e) = bdg+b dfg+b d g+bd eg = bd(f+f )g(e+e ) + b dfg(e+e ) + b d (f+f )g(e+e ) +bd (f+f )ge = bdfg(e+e ) + bdf g(e+e ) + b dfge + b dfge + b d fg(e+e ) + b d f g(e+e ) +bd fge + bd f ge = bdfge + bdfge + bdf ge + bdf ge + b dfge + b dfge + b d fge + b d fge + b d f ge + b d f ge +bd fge + bd f ge = Σ m(11111, 11110, 11011, 11010, 01111, 01110, 00111, 00110, 00011, 00010, 10111, 10011) = Σ m(00010, 00011, 00110, 00111, 01110, 01111, 10011, 10111,11010, 11011, 11110, 11111) Σ m(2, 3, 6, 7, 14, 15, 19, 23, 26, 27, 30, 31) (2,3) 0001_ (2,6) 00_10 Page 2 of 17

3 (3,7) 00_11 (3,19) _0011 (6,7) 0011_ (6,14) 0_ (7,15) 0_111 (7,23) _0111 (14,15) 0111_ (14,30) _1110 (19,23) 10_11 (19,27) 1_011 (26,27) 1101_ (26,30) 11_ (15,31) _1111 (23,31) 1_111 (27,31) 11_11 (30,31) 1111_ (2,3,6,7) 00_1_ (3,7,19,23) _0_11 (6,7,14,15) 0_11_ (7,15,23,31) 111 (14,15,30,31) _ 111 _ (19,23,27,31) 1 11 (26,27,30,31) 11_ 1_ Prime implicants are: {b d g, d ge, b fg, fge, dfg, bge, bdg} Page 3 of 17

4 Implicant table: f(b,d,f,g,e) = Σ m(00010, 00011, 00110, 00111, 01110, 01111, 10011, 10111,11010, 11011, 11110, 11111) _1_ _0_11 0_11_ 111 _ 111_ _ 1_ Essential prime implicants are: 00_1_ and 11_1_. Minimal cover is: f(b,d,f,g,e) = b d g + d ge + dfg + bdg b) Factored form is: g(d(b+f)+d (b +e)) c) Decomposition: f = gx x = d(b+f)+d (b +e) Page 4 of 17

5 Question 2: Application of Boolean Theory (10 marks) Consider the following three Boolean functions: F(a,b,c,d) = m(2,3,5,7,8,9,10,11,13,15), G(a,b,c, d) = m(2, 3,5,6, 7,10,11,14,15) and H(a,b,c,d) = m(6,7,8,9,13,14,15). a) While considering each of the functions individually, find their minimal cover using Karnaugh Maps. How many logic gates you would need to use to implement the minimal covers of F, G and H? b) Again, minimize the three functions F, G and H using K-Maps. However, this time treat the problem as a 4-input (a,b,c,d) and three output (F,G,H) system. How many gates would you need to implement the system now? Hint: In the three individual K-Maps of functions F, G and H try to identify as common terms to at least two and possibly all three functions, and then share these terms in the covers of F, G and H. Solution a) The solution requires 10 gates and 25 gate inputs. Page 5 of 17

6 c) The 4-input (A,B,C,D) and three output (F,G,H) system requires 8 gates and 22 gate inputs. Page 6 of 17

7 (Question 2 continued ) Page 7 of 17

8 Question 3: CMOS Circuit Technology Design (10 marks) Design a CMOS logic gate that implements the function: F = (A + C)(A + D)(B + D)(C + D). First manipulate the original Boolean expression of the function F, such that the resulting implementation will have the minimal number of transistors. Draw the schematic, indicating which transistors belong to the pull-up and which to the pull-down network. Solution F = (A + C)(A + D)(B + D)(C + D) =(A + C) + (A + D) + (B + D) + (C + D) = AC + AD+ BD+ CD = A(C + D) + D(B + C). Figure 1: CMOS Implementation Page 8 of 17

9 (Question 3 continued ) Page 9 of 17

10 Question 4: VHDL (10 marks) Consider a logic operator that can be either a buffer or an inverter. If a mode select line called MODE_CNTRL is set to 0, then the output SIG_OUT equals the inverse of the input SIG_IN. If MODE_CNTRL is set to 1, then the output SIG_OUT equals the input SIG_IN. a) Write a complete VHDL description using concurrent signal assignments of your choice. b) Rewrite the VHDL code. This time, create components describing a buffer, an inverter, and other needed hardware elements. Then write the complete description using your components. Page 10 of 17

11 (Question 4 continued ) Page 11 of 17

Question 5: Circuit Implementation Strategies (15 marks) Consider the two functions F and G, given in the form of a minimal SoP: F(W,X,Y,Z) =W Y + XYZ and G(W,X,Y,Z) =W XY + XZ +W YZ.

12 Question 5: Circuit Implementation Strategies (15 marks) Consider the two functions F and G, given in the form of a minimal SoP: F(W,X,Y,Z) =W Y + XYZ and G(W,X,Y,Z) =W XY + XZ +W YZ. a) Implement the above two functions using ROM. b) Implement F and G with PLA using no more than four terms. c) Implement F and G with PAL. Solution a) The function is not in the form of the sum of minterms. First, we need to find its minterm representation. F(W, X,Y,Z) = m(5,8,9,12,13), G(W, X,Y, Z) = m(1, 3,5,8,9,11), Figure 2: ROM Implementation For PAL, we need to find a sum of products solution that uses only four different terms. The map below shows such a solution. Page 12 of 17

13 The PAL below implements this four-term solution. Figure 3: PLA Implementation PAL implementation is straight forward, as there are no restrictions on the hardware. For the implementation we use the minimized functions from part b). Page 13 of 17

14 (question 5 continued ) Page 14 of 17

15 Question 6: Circuit Implementation Strategies LUT (5 marks) Implement the following 6-variable function Z(a,b,c,d,e, f ) = abcde f + abcde f + bcde f using 4-input LUTs. List inside each LUT the truth table it realizes. Solution As the original function is of 6 variables we need to perform the Shannon decomposition to reduce the variable count. The first variable of the decomposition is a: Z = a Z 0 + az 1. Z 0 = 0bcd ef + 1b c def + b cde f = b c def + b cde f. Z 1 = 1bcd ef + 0b c def + b cde f = bcd ef + b cde f. Next, Z0 and Z1 are expanded around variable b. Z 00 is obtained by substituting 0 for b in Z 0 Z 00 = 1c def + 1cde f = c def + cde f. Z 01 is obtained by substituting 1 for b in Z 0 : Z 01 = 0c def + 0cde f = 0. Z 10 is obtained by substituting 0 for b in Z 1 : Z 10 = 0cd ef + 1cde f = cde f. Z 11 is obtained by substituting 1 for b in Z 1 : Z 11 = 1cd ef + 0cde f = cd ef. Now Z can be written as: Z = a Z 0 + az 1, Z 0 = b Z 00 + bz 01, Z 1 = b Z 10 + bz 11. Page 15 of 17

16 Figure 4: LUT Implementation Note that each LUT implements the AND functions, so the contents of each LUT is 15 0 and last 1. Page 16 of 17

17 (question 6 continued ) Page 17 of 17

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,