ECE232: Hardware Organization and Design

Transcription

1 ECE232: Hardware Organization and Design Lecture 14: One Cycle MIPs Datapath Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

2 R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result rd rs * rt * = { add, sub, AND, OR, slt } 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 ECE331: One Cycle MIPs Datapath 2

3 Load/Store Instructions Read register operands Calculate address using 16-bit offset Use ALU, but sign-extend offset Load (35): Read memory and update register Store (43): Write register value to memory lw rt, offset(rs) sw rt, offset(rs) 35 or 43 rs rt address 31:26 25:21 20:16 15:0 ECE331: One Cycle MIPs Datapath 3

4 Branch Instructions Read register operands Compare operands Use ALU, subtract and check Zero output Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetch 4 rs rt address 31:26 25:21 20:16 15:0 beq rs, rt, address ECE331: One Cycle MIPs Datapath 4

5 Branch Instructions Just re-routes wires Sign-bit wire replicated ECE331: One Cycle MIPs Datapath 5

6 Composing the Elements First-cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions Instruction Fetch Decode, Inc PC and Read Registers ALU Operation, Branch address Data Memory operation Write Back ECE331: One Cycle MIPs Datapath 6

7 R-Type/Load/Store Datapath ECE331: One Cycle MIPs Datapath 7

8 Full Datapath ECE331: One Cycle MIPs Datapath 8

9 Defining Control op rs rt rd shamt funct 6 6 R-format instruction Control Logic To datapath ECE331: One Cycle MIPs Datapath 9

10 Defining Control Note that funct field only present in R-format instruction - funct controls ALU only To simplify control, define Main, ALU control separately using multiple levels will also increase speed important optimization technique ALUop inputs will be defined op funct Control Logic op Main Control ALUop ALU control ALUcon funct ECE331: One Cycle MIPs Datapath 10

11 ALU Control ALU used for Load/Store: Funct = add Branch: Funct = subtract R-type: Function depends on funct field ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR ECE331: One Cycle MIPs Datapath 11

12 ALU Control Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add add 0010 subtract subtract 0110 AND AND 0000 OR OR 0001 set-on-lessthan set-on-lessthan 0111 ECE331: One Cycle MIPs Datapath 12

13 The Main Control Unit Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read read, except for load write for R-type and load sign-extend and add ECE331: One Cycle MIPs Datapath 13

14 Datapath With Control op rs rt rd addr/ func ECE331: One Cycle MIPs Datapath 14

15 R-Type Instruction op rs rt rd func ECE331: One Cycle MIPs Datapath 15

16 Load Instruction op rs rt addr ECE331: One Cycle MIPs Datapath 16

17 Branch-on-Equal Instruction op rs rt addr ECE331: One Cycle MIPs Datapath 17

18 Implementing Jumps Jump 2 address 31:26 25:0 Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00 Need an extra control signal decoded from opcode j address ECE331: One Cycle MIPs Datapath 18

19 Datapath With Jumps Added op ECE331: One Cycle MIPs Datapath 19

20 Datapath With Control op rs rt rd addr/ func ECE331: One Cycle MIPs Datapath 20

21 R-Format Instruction: add $t1, $t2, $t3 op rs rt rd addr/ func Memto- Reg Mem Mem Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0 R-format ECE331: One Cycle MIPs Datapath 21

22 Load Instruction op rs rt rd addr/ func Instruction RegDst ALUSrc Memto- Reg Reg Write Mem Read Mem Write Branch ALUOp1 ALUp0 lw ECE331: One Cycle MIPs Datapath 22

23 Branch-on-Equal Instruction op rs rt rd addr/ func Instruction RegDst ALUSrc Memto- Reg Reg Write Mem Read Mem Write Branch ALUOp1 ALUp0 beq x 0 x ECE331: One Cycle MIPs Datapath 23

24 Simple combinational logic Memto- Reg Mem Mem Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0 R-format lw sw X 1 X beq X 0 X I n p u t s O p 5 O p 4 O p 3 O p 2 O p 1 O p 0 R - f o r m a t I w s w b e q O u t p u t s R e g D s t A L U S r c M e m t o R e g R e g W r i t e M e m R e a d M e m W r i t e B r a n c h A L U O p 1 ECE331: One Cycle MIPs Datapath 24 A L U O p O

25 Summary Understanding the MIPs datapath requires effort You need to carefully read the text in addition to examining the lecture slides Processor built from primitive components ALU, memory, registers, muxes, etc The operation of these components is manipulated by control logic. The output of the control logic is different for every instruction. You should familiarize yourself with the control signals for each instruction For each instruction ask yourself which portions of the datapath should be used Then examine the control signals to prove to yourself that the correct signals are generated Presented architecture operates in a single clock cycle Multicycle pipelined datapath coming next! ECE331: One Cycle MIPs Datapath 25