ECE 313 Computer Organization EXAM 2 November 11, 2000
|
|
- Adela Clark
- 5 years ago
- Views:
Transcription
1 This exam is open book and open notes. You have 50 minutes. Credit for problems requiring calculation will be given only if you show your work. 1. ALU Design / Logic Operations 20 Points The subset of the MIPS instruction set that is supported by the ALU design in Chapter 4 includes two bitwise Boolean operations: AND and OR. The full MIPS architecture specifies also the NOR, NOT, and Exclusive OR (XOR) operations. In this problem we will consider using a four-to-one multiplexer as a universal function unit, as shown here: Control Inputs C0 C1 C2 C3 Data Inputs Ai Bi Yi Data Output In this circuit the select inputs of the multiplexer are treated as data signals, where each possible value of A i and B i selects a control input value C0, C1, C2, or C3. By setting the control inputs to different values, we can make the function unit perform an arbitrary boolean function of the two inputs A i and B i. As shown in the example above, making the inputs C0=0, C1=0, C2=0, and C3=1 makes the output Y i =1 only when A i =1 and B i =1. This computers an AND function, as shown in the table below. Similarly, making the inputs C0=0, C1=1, C2=1, and C3=1 makes the output Y i =1 whenever either A i =1 or B i =1. This computes an OR function. (a) Fill in the rest of the table below to show how the function unit could be used to compute the logic functions A i NOR B i, NOT A i, and A i XOR B i. Function C0 C1 C2 C3 AND OR NOR NOT Ai XOR Page 1 of 6
2 (b) Redesign the 1-bit ALU slice shown in Figure 4.16 of the book (p. 236) using the function unit to replace the AND and OR gates that perform logic functions, allowing the ALU to perform the additional MIPS boolean instructions. Draw a diagram of your redesigned circuit in the space provided below. How many control inputs does the modified ALU have? 2. Floating Point / Logical & Shifting Instructions 20 Points A single-precision IEEE floating-point number is stored a memory location X. Write a sequence of MIPS assembly instructions that will calculate the absolute value of this number and store the result back in memory location X. Accomplish this without using any floating point instructions. Page 2 of 6
3 3. Floating Point Representation 20 Points (a) In the space provided below, show the largest positive number that can be represented in IEEE single-precision floating point. Also, write the power of two (i.e., 2 X ) that most closely represents the value of this number Closest power of two: (b) In the space provided below, show the smallest negative number (where smallest means closest to zero ) that can be represented in IEEE single-precision floating point. Also, write the power of two (i.e., 2 X ) that most closely represents the value of this number Closest power of two: (c) Translate the number shown below in IEEE single-precision floating point format into its decimal equivalent and writes its value in the space provided below Value of number: Page 3 of 6
4 4. Single-Cycle Processor Design 20 Points Modify the single-cycle datapath and control to implement the jr (jump register) instruction. The register transfer description for this instruction is as follows: PC <- Reg[rs] Mark the necessary changes to the datapath and control on the diagrams shown below. (See Book Figure 5.33, p. 383) Instruction RegDst ALUSrc MemtoReg Reg Write Control Table Mem Read Mem Write Branch ALUOp1 ALUOp0 jr Page 4 of 6
5 5. Multi-Cycle Processor Design 20 Points Modify the multi-cycle processor datapath and control to implement the jr (jump register) instruction. The register transfer description is the same as in the previous problem. Mark your changes on the attached schematic diagram and state diagram. How many clock cycles are required to execute the jump register instruction? (See Book Figure 5.33, p. 383) Page 5 of 6
6 Multicycle Design State Diagram (see Book Fig. 5.42, p. 396) Page 6 of 6
ECE 313 Computer Organization FINAL EXAM December 13, 2000
This exam is open book and open notes. You have until 11:00AM. Credit for problems requiring calculation will be given only if you show your work. 1. Floating Point Representation / MIPS Assembly Language
More informationECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.
This exam is open book and open notes. You have 2 hours. Problems 1-4 refer to a proposed MIPS instruction lwu (load word - update) which implements update addressing an addressing mode that is used in
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationCS 2506 Computer Organization II Test 1. Do not start the test until instructed to do so! printed
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted one-page formula sheet. No calculators or other computing devices may
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 14: One Cycle MIPs Datapath Adapted from Computer Organization and Design, Patterson & Hennessy, UCB R-Format Instructions Read two register operands Perform
More information4. What is the average CPI of a 1.4 GHz machine that executes 12.5 million instructions in 12 seconds?
Chapter 4: Assessing and Understanding Performance 1. Define response (execution) time. 2. Define throughput. 3. Describe why using the clock rate of a processor is a bad way to measure performance. Provide
More informationSystems Architecture
Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software
More informationCSE 378 Midterm 2/12/10 Sample Solution
Question 1. (6 points) (a) Rewrite the instruction sub $v0,$t8,$a2 using absolute register numbers instead of symbolic names (i.e., if the instruction contained $at, you would rewrite that as $1.) sub
More informationAdding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20)
Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20) The MIPS jump and link instruction, jal is used to support procedure calls by jumping to jump address (similar to j ) and
More informationDigital Design & Computer Architecture (E85) D. Money Harris Fall 2007
Digital Design & Computer Architecture (E85) D. Money Harris Fall 2007 Final Exam This is a closed-book take-home exam. You are permitted a calculator and two 8.5x sheets of paper with notes. The exam
More informationCOMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
More informationCSEN 601: Computer System Architecture Summer 2014
CSEN 601: Computer System Architecture Summer 2014 Practice Assignment 5 Solutions Exercise 5-1: (Midterm Spring 2013) a. What are the values of the control signals (except ALUOp) for each of the following
More informationChapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
More informationChapter 5 Solutions: For More Practice
Chapter 5 Solutions: For More Practice 1 Chapter 5 Solutions: For More Practice 5.4 Fetching, reading registers, and writing the destination register takes a total of 300ps for both floating point add/subtract
More informationProject Description EEC 483 Computer Organization, Spring 2019
Project Description EEC 483 Computer Organization, Spring 2019 Title: Implement a (single-cycle) MIPS processor on Altera DE10-Lite using Quartus and VHDL Goal: This project is designed to help understand
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationDesign of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
More informationWinter 2006 FINAL EXAMINATION Auxiliary Gymnasium Tuesday, April 18 7:00pm to 10:00pm
University of Calgary Department of Electrical and Computer Engineering ENCM 369: Computer Organization Lecture Instructor for L01 and L02: Dr. S. A. Norman Winter 2006 FINAL EXAMINATION Auxiliary Gymnasium
More informationCS 351 Exam 2 Mon. 11/2/2015
CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front
More informationCSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation
CSE 2021: Computer Organization Fall 2010 Solution to Assignment # 3: Multicycle Implementation Note that these questions are taken from the previous final exmas of CSE2021 and should serve as practice
More informationECE 313 Computer Organization FINAL EXAM December 11, Multicycle Processor Design 30 Points
This exam is open book and open notes. Credit for problems requiring calculation will be given only if you show your work. 1. Multicycle Processor Design 0 Points In our discussion of exceptions in the
More informationComputer Organization and Structure
Computer Organization and Structure 1. Assuming the following repeating pattern (e.g., in a loop) of branch outcomes: Branch outcomes a. T, T, NT, T b. T, T, T, NT, NT Homework #4 Due: 2014/12/9 a. What
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationLecture 8: Control COS / ELE 375. Computer Architecture and Organization. Princeton University Fall Prof. David August
Lecture 8: Control COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Datapath and Control Datapath The collection of state elements, computation elements,
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More informationECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationTopic #6. Processor Design
Topic #6 Processor Design Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between
More informationEECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM
More informationCSE 2021 COMPUTER ORGANIZATION
CSE 22 COMPUTER ORGANIZATION HUGH CHESSER CHESSER HUGH CSEB 2U 2U CSEB Agenda Topics:. Sample Exam/Quiz Q - Review 2. Multiple cycle implementation Patterson: Section 4.5 Reminder: Quiz #2 Next Wednesday
More informationProblem 4 The order, from easiest to hardest, is Bit Equal, Split Register, Replace Under Mask.
HW3 Solutions (CS552 Spring 2013) Grade distribution: (Total: 100) - Verilog submission of problems 1), 2) and 3) carry 15 points each(total: 45 points) - Written part of problem 1), 2) and 3) carry 5
More informationLecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
Lecture Topics Today: Single-Cycle Processors (P&H 4.1-4.4) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1 Exam #1 Wednesday, 2/15 (3:00-4:20
More informationInf2C - Computer Systems Lecture Processor Design Single Cycle
Inf2C - Computer Systems Lecture 10-11 Processor Design Single Cycle Boris Grot School of Informatics University of Edinburgh Previous lectures Combinational circuits Combinations of gates (INV, AND, OR,
More informationCS 351 Exam 2, Fall 2012
CS 351 Exam 2, Fall 2012 Your name: Rules You may use one handwritten 8.5 x 11 cheat sheet (front and back). This is the only resource you may consult during this exam. Include explanations and comments
More information2. (3 pts) There are two different ways to measure performance. What are they? 3. (3 pts) Why doesn t MIPS have a subtract immediate instruction?
1. (3 pts) What is Amdahl s law, inwords? 2. (3 pts) There are two different ways to measure performance. What are they? 3. (3 pts) Why doesn t MIPS have a subtract immediate instruction? 4. (3 pts) Are
More informationcs470 - Computer Architecture 1 Spring 2002 Final Exam open books, open notes
1 of 7 ay 13, 2002 v2 Spring 2002 Final Exam open books, open notes Starts: 7:30 pm Ends: 9:30 pm Name: (please print) ID: Problem ax points Your mark Comments 1 10 5+5 2 40 10+5+5+10+10 3 15 5+10 4 10
More informationDepartment of Electrical Engineering and Computer Sciences Fall 2003 Instructor: Dave Patterson CS 152 Exam #1. Personal Information
University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2003 Instructor: Dave Patterson 2003-10-8 CS 152 Exam #1 Personal Information First
More informationMcGill University Faculty of Engineering FINAL EXAMINATION Fall 2007 (DEC 2007)
McGill University Faculty of Engineering FINAL EXAMINATION Fall 2007 (DEC 2007) VERSION 1 Examiner: Professor T.Arbel Signature: INTRODUCTION TO COMPUTER ENGINEERING ECSE-221A 6 December 2007, 1400-1700
More informationCC 311- Computer Architecture. The Processor - Control
CC 311- Computer Architecture The Processor - Control Control Unit Functions: Instruction code Control Unit Control Signals Select operations to be performed (ALU, read/write, etc.) Control data flow (multiplexor
More informationLecture 4: Review of MIPS. Instruction formats, impl. of control and datapath, pipelined impl.
Lecture 4: Review of MIPS Instruction formats, impl. of control and datapath, pipelined impl. 1 MIPS Instruction Types Data transfer: Load and store Integer arithmetic/logic Floating point arithmetic Control
More informationCPS 104 Final Exam. 2pm to 5pm Open book exam. Answer all questions, state all your assumptions, clearly mark your final answer. 1.
CPS 104 Final Exam 2pm to 5pm Open book exam Answer all questions, state all your assumptions, clearly mark your final answer. Be sure you have all eight (8) pages of the exam. Write your name on each
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationMidterm I October 6, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID
More informationTHE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination
THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination May 23, 2014 Name: Email: Student ID: Lab Section Number: Instructions: 1. This
More informationGuerrilla Session 3: MIPS CPU
CS61C Summer 2015 Guerrilla Session 3: MIPS CPU Problem 1: swai (Sp04 Final): We want to implement a new I- type instruction swai (store word then auto- increment). The operation performs the regular sw
More informationECE Exam I - Solutions February 19 th, :00 pm 4:25pm
ECE 3056 Exam I - Solutions February 19 th, 2015 3:00 pm 4:25pm 1. (35 pts) Consider the following block of SPIM code. The text segment starts at 0x00400000 and the data segment starts at 0x10010000..data
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationChapter 5: The Processor: Datapath and Control
Chapter 5: The Processor: Datapath and Control Overview Logic Design Conventions Building a Datapath and Control Unit Different Implementations of MIPS instruction set A simple implementation of a processor
More informationPoints available Your marks Total 100
CSSE 3 Computer Architecture I Rose-Hulman Institute of Technology Computer Science and Software Engineering Department Exam Name: Section: 3 This exam is closed book. You are allowed to use the reference
More informationECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationEECS 151/251A Fall 2017 Digital Design and Integrated Circuits. Instructor: John Wawrzynek and Nicholas Weaver. Lecture 13 EE141
EECS 151/251A Fall 2017 Digital Design and Integrated Circuits Instructor: John Wawrzynek and Nicholas Weaver Lecture 13 Project Introduction You will design and optimize a RISC-V processor Phase 1: Design
More informationECE369. Chapter 5 ECE369
Chapter 5 1 State Elements Unclocked vs. Clocked Clocks used in synchronous logic Clocks are needed in sequential logic to decide when an element that contains state should be updated. State element 1
More informationFor More Practice FMP
FMP 5.13-1 Single Cycle Datapaths with Floating Point 5.4 [5] < 5.4> Suppose we have a floating-point unit that requires 400 ps for a floating-point add and 600 ps for a floating-point multiply, not including
More informationComputer Architecture V Fall Practice Exam Questions
Computer Architecture V22.0436 Fall 2002 Practice Exam Questions These are practice exam questions for the material covered since the mid-term exam. Please note that the final exam is cumulative. See the
More informationECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.
This exam is open book and open notes. You have 2 hours. Problems 1-5 refer to the following: We wish to add a new R-Format instruction to the MIPS Instruction Set Architecture called l_inc (load and increment).
More informationCS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science A simple MIPS We will design a simple MIPS processor that supports a small instruction
More informationCS/COE0447: Computer Organization
A simple MIPS CS/COE447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science We will design a simple MIPS processor that supports a small instruction
More informationSingle Cycle Data Path
Single ycle ata Path S 365 Lecture 6 Prof. Yih Huang S365 1 MIPS Lite We're ready to look at an implementation of the MIPS Simplified to support only: memory-reference instructions: lw, sw arithmetic-logical
More informationMachine Organization & Assembly Language
Name: CSE 378 Winter 29 Machine Organization & Assembly Language Midterm Exam Solution your answers on these pages. itional pages may be attached (with staple) if necessary. Please ensure that your answers
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationNATIONAL UNIVERSITY OF SINGAPORE
NATIONAL UNIVERSITY OF SINGAPORE SCHOOL OF COMPUTING EXAMINATION FOR Semester 1 AY2013/14 CS2100 COMPUTER ORGANISATION ANSWER SCRIPT Nov 2013 Time allowed: 2 hours Caveat on the grading scheme: I have
More informationCSE Computer Architecture I Fall 2009 Lecture 13 In Class Notes and Problems October 6, 2009
CSE 30321 Computer Architecture I Fall 2009 Lecture 13 In Class Notes and Problems October 6, 2009 Question 1: First, we briefly review the notion of a clock cycle (CC). Generally speaking a CC is the
More informationCSE 2021 COMPUTER ORGANIZATION
CSE 2021 COMPUTER ORGANIZATION HUGH LAS CHESSER 1012U HUGH CHESSER CSEB 1012U W10-M Agenda Topics: 1. Multiple cycle implementation review 2. State Machine 3. Control Unit implementation for Multi-cycle
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationCSE Lecture In Class Example Handout
CSE 30321 Lecture 10-11 In Class Example Handout Question 1: First, we briefly review the notion of a clock cycle (CC). Generally speaking a CC is the amount of time required for (i) a set of inputs to
More informationSolution printed. Do not start the test until instructed to do so! CS 2504 Intro Computer Organization Test 2 Spring 2006.
VIRG INIA POLYTECHNIC INSTITUTE AND STATE U T PROSI M UNI VERSI TY Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted
More informationThe Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
More informationLECTURE 5. Single-Cycle Datapath and Control
LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.
More informationWinter 2002 FINAL EXAMINATION
University of Calgary Department of Electrical and Computer Engineering ENCM 369: Computer Organization Instructors: Dr. S. A. Norman (L01) and Dr. S. Yanushkevich (L02) Note for Winter 2005 students Winter
More information4. (2 pts) What is the only valid and unimpeachable measure of performance?
1. (2 pts) What concept is at the heart of RISC processing? 2. (2 pts) What are the two main ways to define performance? 3. (3 pts) What is Amdahl s law, inwords? 4. (2 pts) What is the only valid and
More informationﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control
معماري كامپيوتر پيشرفته معماري MIPS data path and control abbasi@basu.ac.ir Topics Building a datapath support a subset of the MIPS-I instruction-set A single cycle processor datapath all instruction actions
More informationEE 457 Unit 6a. Basic Pipelining Techniques
EE 47 Unit 6a Basic Pipelining Techniques 2 Pipelining Introduction Consider a drink bottling plant Filling the bottle = 3 sec. Placing the cap = 3 sec. Labeling = 3 sec. Would you want Machine = Does
More informationSystems Architecture I
Systems Architecture I Topics A Simple Implementation of MIPS * A Multicycle Implementation of MIPS ** *This lecture was derived from material in the text (sec. 5.1-5.3). **This lecture was derived from
More informationFinal Exam Spring 2017
COE 3 / ICS 233 Computer Organization Final Exam Spring 27 Friday, May 9, 27 7:3 AM Computer Engineering Department College of Computer Sciences & Engineering King Fahd University of Petroleum & Minerals
More informationTo design a 4-bit ALU To experimentally check the operation of the ALU
1 Experiment # 11 Design and Implementation of a 4 - bit ALU Objectives: The objectives of this lab are: To design a 4-bit ALU To experimentally check the operation of the ALU Overview An Arithmetic Logic
More informationUniversity of Jordan Computer Engineering Department CPE439: Computer Design Lab
University of Jordan Computer Engineering Department CPE439: Computer Design Lab Experiment : Introduction to Verilogger Pro Objective: The objective of this experiment is to introduce the student to the
More informationECE Sample Final Examination
ECE 3056 Sample Final Examination 1 Overview The following applies to all problems unless otherwise explicitly stated. Consider a 2 GHz MIPS processor with a canonical 5-stage pipeline and 32 general-purpose
More informationComputer Architecture I Midterm I (solutions)
Computer Architecture I Midterm II May 9 2017 Computer Architecture I Midterm I (solutions) Chinese Name: Pinyin Name: E-Mail... @shanghaitech.edu.cn: Question Points Score 1 1 2 23 3 13 4 18 5 14 6 15
More informationCOMP2611: Computer Organization. The Pipelined Processor
COMP2611: Computer Organization The 1 2 Background 2 High-Performance Processors 3 Two techniques for designing high-performance processors by exploiting parallelism: Multiprocessing: parallelism among
More informationUniversity of California, Berkeley College of Engineering
University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2015 Instructors: Vladimir Stojanovic, John Wawrzynek 2015-11-10 L J After the
More informationUniversity of California, Berkeley College of Engineering
University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Summer 25 Instructor: Sagar Karandikar 25-7-28 L J After the exam, indicate on the line
More informationSample Exam I PAC II ANSWERS
Sample Exam I PAC II ANSWERS Please answer questions 1 and 2 on this paper and put all other answers in the blue book. 1. True/False. Please circle the correct response. a. T In the C and assembly calling
More informationThe Processor: Datapath & Control
Chapter Five 1 The Processor: Datapath & Control We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationCPE 335. Basic MIPS Architecture Part II
CPE 335 Computer Organization Basic MIPS Architecture Part II Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE232 Basic MIPS Architecture
More informationCENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu
CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified
More informationECE Exam I February 19 th, :00 pm 4:25pm
ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and
More informationUniversity of California, Berkeley College of Engineering
University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Spring 2016 Instructors: Vladimir Stojanovic, Nicholas Weaver 2016-04-04 L J After the
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More informationLaboratory 5 Processor Datapath
Laboratory 5 Processor Datapath Description of HW Instruction Set Architecture 16 bit data bus 8 bit address bus Starting address of every program = 0 (PC initialized to 0 by a reset to begin execution)
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationLecture 5 and 6. ICS 152 Computer Systems Architecture. Prof. Juan Luis Aragón
ICS 152 Computer Systems Architecture Prof. Juan Luis Aragón Lecture 5 and 6 Multicycle Implementation Introduction to Microprogramming Readings: Sections 5.4 and 5.5 1 Review of Last Lecture We have seen
More informationEE457. Note: Parts of the solutions are extracted from the solutions manual accompanying the text book.
EE457 Instructor: G. Puvvada ======================================================================= Homework 5b, Solution ======================================================================= Note:
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Data Paths and Microprogramming We have spent time looking at the MIPS instruction set architecture and building
More informationECE 313 Computer Organization EXAM 2 November 9, 2001
ECE 33 Computer Organization EA 2 November 9, 2 This exam is open book and open notes. You have 5 minutes. Credit for problems requiring calculation will be given only if you show your work. Choose and
More informationOPEN BOOK, OPEN NOTES. NO COMPUTERS, OR SOLVING PROBLEMS DIRECTLY USING CALCULATORS.
CS/ECE472 Midterm #2 Fall 2008 NAME: Student ID#: OPEN BOOK, OPEN NOTES. NO COMPUTERS, OR SOLVING PROBLEMS DIRECTLY USING CALCULATORS. Your signature is your promise that you have not cheated and will
More informationComputer Architecture, IFE CS and T&CS, 4 th sem. Single-Cycle Architecture
Single-Cycle Architecture Data flow Data flow is synchronized with clock (edge) in sequential systems Architecture Elements - assumptions Program (Instruction) memory: All instructions & buses are 32-bit
More informationSingle Cycle Datapath
Single Cycle atapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili Section 4.1-4.4 Appendices B.3, B.7, B.8, B.11,.2 ing Note: Appendices A-E in the hardcopy text correspond to chapters 7-11 in
More informationNAME: 1a. (10 pts.) Describe the characteristics of numbers for which this floating-point data type is well-suited. Give an example.
MSU CSC 285 Spring, 2007 Exam 2 (5 pgs.) NAME: 1. Suppose that a eight-bit floating-point data type is defined with the eight bits divided into fields as follows, where the bits are numbered with zero
More informationPipelining. lecture 15. MIPS data path and control 3. Five stages of a MIPS (CPU) instruction. - factory assembly line (Henry Ford years ago)
lecture 15 Pipelining MIPS data path and control 3 - factory assembly line (Henry Ford - 100 years ago) - car wash Multicycle model: March 7, 2016 Pipelining - cafeteria -... Main idea: achieve efficiency
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
Page 1 of 13 King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department COE 301 COMPUTER ORGANIZATION ICS 233: COMPUTER ARCHITECTURE & ASSEMBLY
More information