Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei
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1 Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei
2 Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter MIPS and Register File Register Naming convention 2
3 Today s class Register Naming Convention, a review MIPS Arithmetic, Load/store and logical instructions slt and jr instructions Branches and jumps pc relative addressing 3
4 Naming Convention for registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 4
5 Example Compile A[20] += A[8]; address of A[0] is in $s1 5
6 Anatomy of data transfer inst. lw $t0, 5($s1) offset Base register Index register (why?) 6
7 Instructions, so far Translate to machine code A[20] +=A[8]; 7
8 Shifters Two kinds: logical-- value shifted in is always "0" "0" msb lsb "0" arithmetic-- on right shifts, sign extend msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! 8
9 MIPS logical instructions and $1,$2,$3 $1 = $2 & $3 or $1,$2,$3 $1 = $2 $3 nor $1,$2,$3 $1 = ~($2 $3) andi $1,$2,10 $1 = $2 & 10 ori $1,$2,10 $1 = $2 10 sll $1,$2,10 $1 = $2 << 10 srl $1,$2,10 $1 = $2 >> 10 sra $1,$2,10 $1 = $2 >> 10 9
10 A different style Make access to small constant fast Application for(j=0;j<10;j++) A[j]++; Profile analysis shows: In gcc 52% In spice 69% Of arithmetic instructions involve constants op rs rt immediate addi $s4,$s4,4 10
11 A tiny problem What if the immediate value is beyond the range that 16 bits can provide By the way, what is this range? lui $s1,5 $s What if I want to load 5* to $s1? Who is responsible for doing this? MIPS provides $at for such cases 11
12 American Std Code for Info. Interchange (ASCII) 12
13 Load and store bytes lb $t0,0($sp) sb $t1,4($sp) $sp 13
14 Alignment MIPS requires that all words start at addresses that are multiples of 4 bytes Aligned Not Aligned Called Alignment: objects must fall on address that is multiple of their size. Why do we care? 14
15 Endian-ness or Edianess Big Endian: Leftmost byte is word address Little Endian: Rightmost byte is word address little endian msb lsb Big endian
16 MIPS arithmetic instruction format R-type: I-Type: op Rs Rt Rd funct op Rs Rt Immed 16 Type op funct ADDI 10 xx ADDIU 11 xx SLTI 12 xx SLTIU 13 xx ANDI 14 xx ORI 15 xx XORI 16 xx LUI 17 xx Type op funct ADD ADDU SUB SUBU AND OR XOR NOR Type op funct SLT SLTU
17 New instructions lbu $t0,0($s0) lb $t0,0($s0) Extension $t0 94H $s0 94H 17
18 Addition/Subtraction Examples 0X4E + 0X1F 0X4E 0X1F Overflow operation condition result A + B A > 0 B > 0 < 0 A + B A < 0 B < 0 > 0 A - B A > 0 B < 0 < 0 A - B A < 0 B > 0 > 0 18
19 What to do on overflow? Ignore Programmer is responsible for Leave it to OS Either completely takes care of it Or signals the application What does MIPS do? For signed operation (if overflow occurs) it throws an exception It ignores the overflow of unsigned operations 19
20 If an overflow is detected PC -> EPC mfc0 places EPC to a register ($k0 and $k1 are used for such a purpose) Jump to a code which services the interrupt based on the type of the interrupt Resolve the problem Return with an error code Abort program 20
21 More in overflow No means to check if overflow occurs in MIPS Question: How would I indicate that an overflow occur? For signed operations Unsigned operations 21
22 Instructions for making decisions Conditional/Unconditional branches beq bne j Example Compile $s1,$s2, L1 $s3,$s4, L2 L3 if(i == j) f = g + h k; else f = g + h + k; Given i: $s1, j: $s2, f: $s3, g: $s4, h: $s5, and k: $s6 22
23 More examples compile Loop: g += A[i]; i += j; if(i!= h) goto Loop; 23
24 Compile a while loop while (save[j] == k) j += n; Loop: if(save[j]!= k) goto Exit; j += n; goto Loop; Exit: 24
25 Hierarchical Interpretation of an Application (Executable file) Executable File Object Object procedure procedure Basic block Basic block instruction 25
26 New Instructions slt $s1,$s2,$s3 if $s2 < $s3 set $s1 to 1 else set $s1 to 0 jr $s0 jump to the address given by the $s0 26
27 Branches (Conditional) I-Type bne $s0, $s1, Exit Exit What seems to be the problem? 27
28 PC Relative addressing MIPS adds the content of PC to the immediate field to provide a wider range. Why? 50% of conditional branch targets in gcc are smaller than 16 instructions apart from their origin bne $s0, $s1, address PC = (PC + 4) + 4*address What is the range of the branching? What if you need branch farther than that? We will come back to this shortly. 28
29 Unconditional Branches J-Type opcode Target address What range could it provide? Keep in your mind that J-Type is also word address In J-Type 4 upper bits of the PC will be unchanged Do not place the program across the boundary of 256 MB : 64 million instructions 29
30 Final Question bne $s1,$s2, L1 and L1 is beyond [-2 17, 2 17 ] apart from PC 30
31 Function calls and Procedures What is the difference between a function call and a procedure? Leaf versus Recursive What is needed for supporting the procedure calls by hardware? 31
32 Registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 32
33 Instructions jal x (again jal is also word address) $ra= PC + 4 Jump to the address 4*x Instruction type is J with opcode 3 jr $ra Which we have seen already and jump to the instruction whose address is in the register; in this case we have return address register Instruction type is R with opcode 0 and func 8 33
34 Steps for Making a Procedure Call 1. Save necessary values onto stack 2. Assign argument(s), if any $a0 - $a3 for arguments 3. jal call 4. Restore values from stack 34
35 Steps taken by the Callee 1. Acquire the storage resources needed If need any of $s registers, should save them onto the stack, and after use restore them back to the registers 2. Perform the desired task 3. Place the result values in $v0 and $v1 4. jr $ra 35
36 Rules for Procedures Called with a jal instruction, returns with a jr $ra Accepts up to 4 arguments in $a0, $a1, $a2 and $a3 Return value is always in $v0 (and if necessary in $v1) Must follow register conventions (even in functions that only you will call)! 36
37 Hand - Compile Example int leaf(int g,int h,int i,int j){ int f; f = (g + h) (i + j); return f; } 37
38 MIPS memory layout 38
39 Example Hand - compile int leaf(int arg){ int l=10; return l*arg; } main(){ int j; j = leaf(5); } 39
40 Recursive Calls int fact(int n){ if(n <= 1) return 1; return n * fact(n-1); } int fact(int n){ int a; int b; if(n <= 1) return 1; a = fact(n 1); b = n * a; return b; } 40
41 Recursive Calls (Cont d) main(){ int j=fact(3); } fact(3){ a=fact(2); b=3*a; return b; } fact(2){ a=fact(1); b=2*a; return b; } 41
42 How to represent strings Use the beginning of the string for the length (4 bytes) Accompany string with a variable length Use a special character at the end of the string as an indication of string s end (C uses null for that purpose) 42
43 Example Hand compile strcat(char s[], char t[]){ int i,j; i=j=0; while(s[i]!= 0) i++; while((s[i++] = t[j++])!= 0); } 43
44 Some Words about SPIM Comments, Identifiers, Labels, Number representation, Strings, and Special Characters Some assembly directives.text <addr>.data <addr> Mydata:.word 1,2,3.ascii str1.asciiz str2 44
45 System Calls What is a system call? SPIM provides a small set of system calls How does it work? Load syscall code into $v0 Load arguments (if any) into $a0,, $a3 Issue syscall 45
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