MIPS ISA-II: Procedure Calls & Program Assembly

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1 MIPS ISA-II: Procedure Calls & Program Assembly Module Outline Reiew ISA and understand instruction encodings Arithmetic and Logical Instructions Reiew memory organization Memory (data moement) instructions Control flow instructions Procedure/Function calls Program assembly, linking, & encoding (2) 1

2 Reading Reading 2.8, 2.12 Appendix A: A1 - A.6 ( in online text) Practice Problems: 10, 14,23 Goals Understand the binary encoding of complete program executables o o o o o How can procedures be independently compiled and linked (e.g., libraries)? What makes up an executable? How do libraries become part of the executable? What is the role of the ISA in encoding programs? What constitutes the hardware/software interface (3) Procedure Calls Basic functionality Transfer of parameters & control to procedure Transfer of results & control back to the calling program Support for nested procedures What is so hard about this? Consider independently compiled code modules o Where are the inputs? o Where should I place the outputs? o Recall: What do you need to know when you write procedures in C? (4) 2

3 Specifics Where do we pass data Preferably registers à make the common case fast Memory as an oerflow area Nested procedures The stack, $fp, $sp and $ra Saing and restoring machine state Set of rules that deelopers/compilers abide by Which registers can am I permitted to use with no consequence? Caller and callee sae conentions for MIPS (5) Basic Parameter Passing.data arg1:.word 22, 20, 16, 4 arg2:.word 33,34,45,8 Register usage What about nested calls? What about excess arguments? loop:.text addi $t0, $0, 4 moe $t3, $0 moe $t1, $0 moe $t2, $0 beq $t0, $0, exit addi $t0, $t0, -1 lw $a0, arg1($t1) lw $a1, arg2($t2) jal func add $t3, $t3, $0 addi $t1, $t1, 4 addi $t2, $t2, 4 j loop func: sub $0, $a0, $a1 jr $ra exit: --- PC $31 PC $ (6) 3

4 Leaf Procedure Example C code: int leaf_example (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; } Arguments g,, j are passed in $a0,, $a3 f in $s0 (we need to sae $s0 on stack we will see why later) Results are returned in $0, $1 argument registers $a0 $a1 $a2 $a3 procedure $0 result $1 registers (7) Procedure Call Instructions Procedure call: jump and link jal ProcedureLabel Address of following instruction put in $ra Jumps to target address Procedure return: jump register jr $ra Copies $ra to program counter Can also be used for computed jumps o e.g., for case/switch statements Example: (8) 4

5 Leaf Procedure Example MIPS code: leaf_example: addi $sp, $sp, -4 sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra Sae $s0 on stack Procedure body Result Restore $s0 Return (9) Procedure Call Mechanics High Address $fp $sp Old Stack Frame $fp System Wide Memory Map $sp stack arg registers dynamic data New Stack Frame return address Saed registers $gp PC static data text resered $sp local ariables compiler compiler Low Address ISA HW addressing (10) 5

6 Example of the Stack Frame $fp $sp arg 1 arg 2.. callee saed registers caller saed registers local ariables.. $fp $ra $s0-$s9 $a0-$a3 $t0-$t9 Call Sequence 1. place excess arguments 2. sae caller sae registers ($a0-$a3, $t0-$t9) 3. jal 4. allocate stack frame 5. sae callee sae registers ($s0-$s9, $fp, $ra) 6 set frame pointer Return 1. place function argument in $0 2. restore callee sae registers 3. restore $fp 4. pop frame 5. jr $31 (11) Policy of Use Conentions Name Register number Usage $zero 0 the constant alue 0 $0-$1 2-3 alues for results and expression ealuation $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saed $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address (12) 6

7 Summary: Register Usage $a0 $a3: arguments (reg s 4 7) $0, $1: result alues (reg s 2 and 3) $t0 $t9: temporaries Can be oerwritten by callee $s0 $s7: saed Must be saed/restored by callee $gp: global pointer for static data (reg 28) $sp: stack pointer (reg 29) $fp: frame pointer (reg 30) $ra: return address (reg 31) (13) Non-Leaf Procedures Procedures that call other procedures For nested call, caller needs to sae on the stack: Its return address Any arguments and temporaries needed after the call Restore from the stack after the call (14) 7

8 Non-Leaf Procedure Example C code: int fact (int n) { if (n < 1) return f; else return n * fact(n - 1); } Argument n in $a0 Result in $0 (15) Template for a Procedure 1. Allocate stack frame (decrement stack pointer) 2. Sae any registers (callee sae registers) 3. Procedure body (remember some arguments may be on the stack!) 4. Restore registers (callee sae registers) 5. Pop stack frame (increment stack pointer) 6. Return (jr $ra) (16) 8

9 Non-Leaf Procedure Example } int fact (int n) { callee sae if (n < 1) return f; else return n * fact(n - 1); restore (17) Callee sae MIPS code: fact: Termination Check Leaf Node Recursie call Intermediate Node Non-Leaf Procedure Example addi $sp, $sp, -8 # adjust stack for 2 items sw $ra, 4($sp) # sae return address sw $a0, 0($sp) # sae argument slti $t0, $a0, 1 # test for n < 1 beq $t0, $zero, L1 addi $0, $zero, 1 # if so, result is 1 addi $sp, $sp, 8 # pop 2 items from stack jr $ra # and return L1: addi $a0, $a0, -1 # else decrement n jal fact # recursie call lw $a0, 0($sp) # restore original n lw $ra, 4($sp) # and return address addi $sp, $sp, 8 # pop 2 items from stack mul $0, $a0, $0 # multiply to get result jr $ra # and return (18) 9

10 Module Outline Reiew ISA and understand instruction encodings Arithmetic and Logical Instructions Reiew memory organization Memory (data moement) instructions Control flow instructions Procedure/Function calls Program assembly, linking, & encoding (19) The Complete Picture C program Reading: 2.12, A2, A3, A4, A5 compiler Assembly assembler Object module Object library linker executable loader memory (20) 10

11 Create a binary encoding of all natie instructions Translation of all pseudo-instructions The Assembler Computation of all branch offsets and jump addresses Symbol table for unresoled (library) references Create an object file with all pertinent information Header (information) Text segment Data segment Relocation information Example: Symbol table (21) One pass s. two pass assembly Effect of fixed s. ariable length instructions Time, space and one pass assembly Assembly Process Local labels, global labels, external labels and the symbol table What does mean when a symbol is unresoled? Absolute addresses and re-location (22) 11

12 Example.data L1:.word 0x44,22,33,55 # array main: loop:.text.globl main la $t0, L1 li $t1, 4 add $t2, $t2, $zero lw $t3, 0($t0) add $t2, $t2, $t3 addi $t0, $t0, 4 addi $t1, $t1, -1 bne $t1, $zero, loop What changes when you relocate code? ] 3c lui $8, 4097 [L1] [ ] ori $9, $0, 4 [ ] add $10, $10, $0 [ c] 8d0b0000 lw $11, 0($8) [ ] 014b5020 add $10, $10, $11 [ ] addi $8, $8, 4 [ ] 2129ffff addi $9, $9, -1 [ c] 1520fffc bne $9, $0, -16 [loop-0x c] [ ] 000a082a slt $1, $0, $10 [ ] bne $1, $0, 12 [then-0x ] [ ] 000a8021 addu $16, $0, $10 [ c] d j 0x [exit] [ ] 000a8821 addu $17, $0, $10 [ ] a ori $2, $0, 10 [ ] c syscall bgt $t2, $0, then moe $s0, $t2 j exit then: moe $s1, $t2 exit: li $0, 10 syscall Assembly Program Natie Instructions Assembled Binary (23) Linker Links independently compiled modules Determines real addresses Linker & Loader Updates the executables with real addresses Loader As the name implies Specifics are operating system dependent (24) 12

13 Program A Assembly A Program B Assembly B cross reference labels Linking header text static data reloc symbol table debug Why do we need independent compilation? What are the issues with respect to independent compilation? references across files (can be to data or code!) absolute addresses and relocation Study: Example on pg. 127 (25) # separate file Example:.text 0x addi $4, $0, 4 0x addi $5, $0, jal func_add done 0x a 0x c # separate file.text.globl func_add func_add: add $2, $4, $5 0x jr $31 0x03e x x x x x ? 0x c 0x a 0x x c 0x x x x03e00008 Ans: 0x0c (26) 13

14 Loading a Program Load from image file on disk into memory 1. Read header to determine segment sizes 2. Create irtual address space (later) 3. Copy text and initialized data into memory o Or set page table entries so they can be faulted in 4. Set up arguments on stack 5. Initialize registers (including $sp, $fp, $gp) 6. Jump to startup routine o Copies arguments to $a0, and calls main o When main returns, do exit syscall (27) Dynamic Linking Static Linking All labels are resoled at link time Link all procedures that may be called by the program Size of executables? Dynamic Linking: Only link/load library procedure when it is called Requires procedure code to be relocatable Aoids image bloat caused by static linking of all (transitiely) referenced libraries Automatically picks up new library ersions (28) 14

15 Lazy Linkage Indirection table Stub: Loads routine ID, Jump to linker/loader Linker/loader code Dynamically mapped code (29) Standard Formats: ELF Executable and Linking Format (ELF) ELF header Program Header Table (optional) Section 1 Section 2 ELF header Program Header Table (required) Segment 1 Segment 2 Section Header Table (required) Linking View Section Header Table (optional) Execution View See wikipedia.org (30) 15

16 Standard Object File Formats There are other formats associated with different operating systems ISA neutral format for building executables Tools Source à assembly à object à executable à process image (31) The Computing Model Reisited Register File (Programmer Visible State) 0x00 0x01 0x02 0x03 Memory Interface stack 0x1F Processor Internal Buses Dynamic Data Data segment (static) Text Segment Program Counter Instruction register Kernel registers Programmer Inisible State Resered 0xFFFFFFFF Arithmetic Logic Unit (ALU) Memory Map Program Execution and the on Neumann model (32) 16

17 Instruction Set Architectures (ISA) Instruction set architectures are characterized by seeral features 1. Operations Types, precision, size 2. Organization of internal storage Stack machine Accumulator General Purpose Registers (GPR) 3. Memory addressing Operand location and addressing (33) Instruction Set Architectures 4. Memory abstractions Segments, irtual address spaces (more later) Memory mapped I/O (later) 5. Control flow Condition codes Types of control transfers conditional s. unconditiional ISA design is the result of many tradeoffs Decisions determine hardware implementation Impact on time, space, and energy Check out ISAs for PowerPC, ARM, x86, SPARC, etc. (34) 17

18 ARM & MIPS Similarities ARM: the most popular embedded core Similar basic set of instructions to MIPS ARM MIPS Date announced Instruction size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data alignment Aligned Aligned Data addressing modes 9 3 Registers bit bit Input/output Memory mapped Memory mapped (35) Compare and Branch in ARM Uses condition codes for result of an arithmetic/logical instruction Negatie, zero, carry, oerflow Compare instructions to set condition codes without keeping the result Each instruction can be conditional Top 4 bits of instruction word: condition alue Can aoid branches oer single instructions Z V C N CPU/Core $0 $1 $31 ALU (36) 18

19 Instruction Encoding Differences? (37) The Intel x86 ISA Eolution with backward compatibility 8080 (1974): 8-bit microprocessor o Accumulator, plus 3 index-register pairs 8086 (1978): 16-bit extension to 8080 o Complex instruction set (CISC) 8087 (1980): floating-point coprocessor o Adds FP instructions and register stack (1982): 24-bit addresses, MMU o Segmented memory mapping and protection (1985): 32-bit extension (now IA-32) o Additional addressing modes and operations o Paged memory mapping as well as segments (38) 19

20 The Intel x86 ISA Further eolution i486 (1989): pipelined, on-chip caches and FPU Pentium (1993): superscalar, 64-bit datapath o Later ersions added MMX (Multi-Media extension) instructions o The infamous FDIV bug Pentium Pro (1995), Pentium II (1997) o New microarchitecture (see Colwell, The Pentium Chronicles) Pentium III (1999) o Added SSE (Streaming SIMD Extensions) and associated registers Pentium 4 (2001) o New microarchitecture o Added SSE2 instructions (39) The Intel x86 ISA And further AMD64 (2003): extended architecture to 64 bits EM64T Extended Memory 64 Technology (2004) o AMD64 adopted by Intel (with refinements) o Added SSE3 instructions Intel Core (2006) o Added SSE4 instructions, irtual machine support AMD64 (announced 2007): SSE5 instructions Intel Adanced Vector Extension (AVX announced 2008) If Intel didn t extend with compatibility, its competitors would! Technical elegance market success Commonly thought of as a Complex Instruction Set Architecture (CISC) (40) 20

21 Basic x86 Registers (41) Basic x86 Addressing Modes Two operands per instruction Source/dest operand Register Register Register Memory Memory Second source operand Register Immediate Memory Register Immediate n Memory addressing modes n Address in register n Address = R base + displacement n Address = R base + 2 scale R index (scale = 0, 1, 2, or 3) n Address = R base + 2 scale R index + displacement (42) 21

22 x86 Instruction Encoding Variable length encoding Postfix bytes specify addressing mode Prefix bytes modify operation o Operand length, repetition, locking, (43) Implementing IA-32 Complex instruction set makes implementation difficult Hardware translates instructions to simpler microoperations o Simple instructions: 1 1 o Complex instructions: 1 many Microengine similar to RISC Market share makes this economically iable Comparable performance to RISC Compilers aoid complex instructions Better code density (44) 22

23 Fallacies Powerful instruction Þ higher performance Fewer instructions required But complex instructions are hard to implement o May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code Þ more errors and less productiity (45) Fallacies Backward compatibility Þ instruction set does not change But they do accrete more instructions x86 instruction set (46) 23

24 Instruction complexity is only one ariable lower instruction count s. higher CPI / lower clock rate Design Principles: simplicity faors regularity smaller is faster good design demands compromise make the common case fast Instruction set architecture a ery important abstraction indeed! Summary (47) Study Guide Compute number of bytes to encode a SPIM program What does it mean for a code segment to be relocatable? Identify addresses that need to be modified when a program is relocated. Gien the new start address modify the necessary addresses Gien the assembly of an independently compiled procedure, ensure that it follows the MIPS calling conentions, modifying it if necessary (48) 24

25 Study Guide (cont.) Gien a SPIM program with nested procedures, ensure that you know what registers are stored in the stack as a consequence of a call Encode/disassemble jal and jr instructions Computation of jal encodings for independently compiled modules How can I make procedure calls faster? Hint: What about a call is it that takes time? How are independently compiled modules linked into a single executable? (assuming one calls a procedure located in another) (49) Glossary Argument registers Caller sae registers Callee sae registers Disassembly Frame pointer Independent compilation Labels: local, global, external Linker/loader Linking: static s. dynamic s. lazy Natie instructions Nested procedures Object file One/two pass assembly Procedure inocation Pseudo instructions Relocatable code Stack frame Stack pointer Symbol table Unresoled symbol (50) 25

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