IWKS 2300/5300 Fall John K. Bennett. Machine Language

Size: px
Start display at page:

Download "IWKS 2300/5300 Fall John K. Bennett. Machine Language"

Transcription

1 IWKS 2300/5300 Fall 2017 John K. Bennett Machine Language

2 Assembly Language / Machine Code Abstraction implementation duality: Assembly language (the instruction set architecture) can be viewed as a (sort-of) programmer-oriented abstraction of the hardware platform The hardware platform represents a physical means for realizing the assembly language / machine code abstraction Assembly Language and Machine Code Statements are Generally One-to-One: Symbolic assembly language statement, e.g., D=A That statement translates into executable binary, e.g., Assembly Language / Machine Code: Roughly speaking, machine code represents an agreed-upon formalism for manipulating data in memory using a processor and (usually) a set of registers. Assembly language syntax can differ widely across different hardware platforms.

3 Machine Code vs. Assembly ADD R1, R2, R3 Evolution: Physical coding Symbolic documentation Symbolic coding Translation and execution Jacquard loom (1801) Assembly requires translation. Augusta Ada King, Countess of Lovelace ( )

4 Some Typical Assembly Language Commands // In what follows R1,R2,R3 are registers, PC is program counter, // and addr is some address in memory. ADD R1,R2,R3 // R1 R2 + R3 ADDI R1,R2,addr // R1 R2 + addr AND R1,R1,R2 JMP addr JEQ R1,R2,addr LOAD R1, addr STORE R1, addr NOP // R1 R1 and R2 (bit-wise) // PC addr // IF R1 == R2 THEN PC addr ELSE PC++ // R1 RAM[addr] // RAM[addr] R1 // Do nothing // Etc. *many* variants

5 Three Address Architecture Consider the following code fragment: X = (A-B) / (C+(D*E)) Load R1, A // R1 Mem[A] Load R2, B // R2 Mem[B] Sub R3, R2, R1 // R3 R2 R1 Load R1, D // R1 Mem[D] Load R2, E // R2 Mem[E] Mpy R4, R1, R2 // R4 R1 * R2 Load R1, C // R1 Mem[C] Add R2, R1, R4 // R2 R1 + R4 Div R1, R3, R2 // R1 R3 / R2 Store X, R1 // Mem[X] R1 There are typically a finite number of registers, on the order of This code: 6 Memory references, code is not compact

6 Two Address Architecture Consider the same code fragment: X = (A-B) / (C+(D*E)) Load R1, A // R1 Mem[A] Load R2, B // R2 Mem[B] Sub R2, R1 // R2 R2 R1 Load R1, D // R1 Mem[D] Load R3, E // R3 Mem[E] Mpy R1, R3 // R1 R1 * R3 Load R4, C // R4 Mem[C] Add R1, R4 // R1 R1 + R4 Div R2, R1 // R2 R2 / R1 Store X, R2 // Mem[X] R2 There are typically a finite number of registers, on the order of This code: 6 Memory references, code is not compact

7 One Address Architecture Consider the following code fragment: X = (A-B) / (C+(D*E)) Load A // Acc Mem[A] Add B // Acc Acc + Mem[B] Store Temp1 // Mem[Temp1] Acc Load D // Acc Mem[D] Mpy E // Acc Acc * Mem[E] Add C // Acc Acc + Mem[C] Store Temp2 // Mem[Temp2] Acc Load Temp1 // Acc Mem[Temp1] Div Temp2 // Acc Acc / Mem[Temp2] Store X // Mem[X] Acc There is one register, called the Accumulator This code: 10 Memory references, code is more compact

8 Zero Address Architecture Consider the following code fragment: X = (A-B) / (C+(D*E)) Push D // SP = SP + 1; Mem[SP] Mem[D]; Push E // SP = SP + 1; Mem[SP] Mem[E]; Mpy // Mem[SP-1] Mem[SP] * Mem[SP-1]; // SP = SP -1 Push C // SP = SP + 1; Mem[SP] Mem[C] Add // Mem[SP-1] Mem[SP] + Mem[SP-1] // SP = SP -1 Push A // SP = SP + 1; Mem[SP] Mem[A] Push B // SP = SP + 1; Mem[SP] Mem[B] Sub // Mem[SP-1] Mem[SP] - Mem[SP-1]; // SP = SP -1 Div // Mem[SP-1] Mem[SP] / Mem[SP-1] Pop X // Mem[X] Mem[SP]; SP = SP Memory references, code is very compact

9 The Hack Computer A 16-bit machine (this means that the ALU and memory width are 16 bits) consisting of the following elements: Data memory: RAM an addressable sequence of registers* Instruction memory: ROM an addressable sequence of registers* Registers: Processing: D, A, M, where M stands for RAM[A] ALU, capable of computing various functions Program counter: PC, holding an address Control: The ROM is loaded with a sequence of 16-bit instructions, one per memory location, beginning at address 0. These instructions are fetched and executed in sequence until a jump instruction is encountered, at which time the PC is set to the jump address. Simple Instruction set: Only two Instructions: A-instruction, C- instruction; A fair amount of complexity is packed into C-instructions * Hack computer only; Recall that real memory is not implemented using registers.

10 The Hack CPU (no control shown) Think of the D Register as the Accumulator

11 The Hack Computer

12 Hack Assembly and VM Code Hack Assembly is a hybrid (1/2 address) code, but has only two kinds of instructions Hack VM is zero address (see IWKS 3300 )

13 Jack Code // Adds var int i, sum; let i =1; let sum = 0; while (i < 101) { let sum = sum + 1; let i = i + 1; } A Hack Machine Language Example

14 A-Instructions // Where value is either a non-negative decimal number // or a symbol referring to such number. value (v = 0 or 1) Binary: 0 v v v v v v v v v v v v v v v Translation to binary: If value represents a non-negative number, see next slide We will handle the case when value is a symbol in Chapter 6 (Assembler).

15 A // A value Where value is either a non-negative number or a symbol referring to a number. Used for: Entering a constant value ( A = value) Coding // A = 17 D = A // D = 17 Selecting a RAM location ( register = // A = 17 D = M // D = RAM[17] Selecting a ROM location ( PC = A // A = 17 JMP // branch to and fetch the // instruction stored in ROM[17]

16 C-Instructions - Lots Going On Symbolic: dest=comp;jump // Either the dest or jump fields may be empty. // If dest is empty, the "=" is ommitted; // If jump is empty, the ";" is omitted. comp dest jump Binary: a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3

17 The Comp Field Determines ALU Output (a and c1-c6) c1-c6 of the Comp Field are identical to ALU control inputs The a bit chooses A or M as the Y input to the ALU (the X ALU input is always D).

18 The A-Register/M Multiplexor (and ALU Out Data Path) D register D x A register A a-bit ALU out address input RAM (selected register) M Mux A/M y PC address input ROM (selected register) Instruction Control Logic Control Signals

19 The Hack CPU (where the control signals go)

20 The Hack Computer

21 A D M The Dest Field Each bit designates a destination (A, D, or M):

22 The Jump Field The effects of j1-j3 are related to the zr and ng ALU output bits: j1 (out < 0): ng j2 (out = 0 ): zr j3 (out > 0): ng NOR zr

23 The C-Instruction Possible Destinations dest = n + s dest = n - s dest = n dest = 0 dest = 1 dest = -1 Exercise 1: Implement the following tasks Using Hack Assembly and Machine Code: Set D to A-1 Set both A and D to A + 1 Set D to 19 Set both A and D to A + D Set RAM[5034] to D - 1 n = {A, D, M} s = {A, D, M, 1} dest = {A, D, M, MD, A, AM, AD, AMD, null} Set RAM[53] to 171 Add 1 to RAM[7], and store the result in D.

24 The C-Instruction dest = x + y dest = x - y dest = x dest = 0 dest = 1 dest = -1 x = {A, D, M} y = {A, D, M, 1} dest = {A, D, M, MD, A, AM, AD, AMD, null} Symbol table: j 3012 sum 4500 q 3812 arr (Symbols and values are arbitrary examples) Exercise 2: Implement the following code using Hack Assembly Language: sum = 0 j = j + 1 q = sum + 12 j arr[3] = -1 arr[j] = 0 arr[j] = 17

25 Control (focus on the yellow chips) D register D A register A a-bit ALU address input RAM (selected register) M Mux A/M In the Hack architecture: ROM = instruction memory PC address input ROM (selected register) Instruction Program = sequence of 16-bit numbers, starting at ROM[0] Current instruction = ROM[PC] To select instruction n from the ROM, we set A to n, using the

26 Handling A-Register Conflicts The Hack programmer can use the A register to select either a data memory location for a subsequent C- instruction involving M, or an instruction memory location for a subsequent C-instruction involving a jump. Thus, to prevent conflicting use of the A register, in wellwritten Hack programs, a C-instruction may contain nonzero j bits (indicating a jump), OR the d3 bit can be set (indicating a reference to M), but not both.

27 Coding Example Exercise 3: Implement the following code using Hack Assembly Language: goto 50 if D==0 goto 112 if D<9 goto 507 if RAM[12] > 0 goto 50 if sum>0 goto END if x[i]<=0 goto NEXT. Symbol table: sum 2200 x 4000 i 15 END 50 NEXT 120 Hack convention: (All symbols and values in are arbitrary examples) True is represented by -1 Hack commands: // set A to value C-command: dest = comp ; jump // dest = and ;jump // are optional Where: comp = 0, 1, -1, D, A,!D,!A, -D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, D A, M,!M, -M,M+1, M-1, D+M, D-M, M-D, D&M, D M dest = M, D, MD, A, AM, AD, AMD, or null jump = JGT, JEQ, JGE, JLT, JNE, JLE, JMP, or null In the command dest = comp; jump, the jump materialzes if (comp jump 0) is true. For example, in D=D+1,JLT, we jump if D+1 < 0. False is represented by 0

28 Hack If logic High level: if condition { code block 1} else { code block 2} code block 3 Hack: D not D;JEQ code block 0;JMP (IF_TRUE) code block 1 (END) Hack convention: code block 3 True is represented by -1 False is represented by 0

29 Hack While Logic High level: while condition { code block 1 } Code block 2 Hack: (LOOP) D not D;JEQ code block 0;JMP (END) code block 2 Hack convention: True is represented by -1 False is represented by 0

30 Complete program example C language code: Hack assembly code: // Adds int i = 1; int sum = 0; while (i <= 100){ sum += i; i++; } Hack assembly convention: Variables: lower-case Labels: upper-case Commands: upper-case // Adds // i refers to some RAM location M=1 // // sum refers to some RAM location M=0 // sum=0 D=M // D = D=D-A // D = i - D;JGT // If (i-100) > 0 goto D=M // D = M=D+M // sum += M=M+1 // 0;JMP // Got LOOP 0;JMP // Infinite loop

31 add.jack // JKB /** Computes the sum of the first 100 integers. */ class Main { function void main() { var int i, sum; let i =1; let sum = 0; } } while (i < 101) { let sum = sum + i; let i = i + 1; } do Output.printString("THE SUM IS: "); do Output.printInt(sum); do Output.println(); return;

32 Symbols in Hack assembly programs Symbols created by Hack programmers and code generators: Label symbols: Used to label destinations of goto commands. Declared by the pseudo command (label). This directive defines the symbol label to refer to the instruction memory location holding the next command in the program (within the program, label is called label ) Variable symbols: Any user-defined symbol label appearing in an assembly program that is not defined elsewhere using the (label) directive is treated as a variable, and is automatically assigned a unique RAM address, starting at RAM address 16 By convention, Hack programmers use lower-case and upper-case letters for variable names and labels, respectively. Predefined symbols: I/O pointers: The symbols SCREEN and KBD are automatically predefined to refer to RAM addresses and 24576, respectively (base addresses of the Hack platform s screen and keyboard memory maps) Virtual registers: covered in future lectures. VM control registers: covered in future lectures. Q: What does the assignment of symbols to RAM addresses? A: The assembler, which is the program that translates symbolic Hack programs into binary Hack program. As part of the translation process, the symbols are resolved to RAM addresses. // Typical symbolic // Hack code, meaning // not M=D A=M D;JGT 0;JMP

33 Hack is a simple machine language Perspective User friendly syntax: D=D+A instead of ADD D,D,A Hack is a ½-address machine : any operation that needs to operate on the RAM must be specified using two commands: an A-command to address the RAM, and a subsequent C-command to operate on it The Hack assembler will be discusses and developed in Chapter 6 A Macro-language could be developed

34 Exercise 1 Implement the following operations using both Hack Assembly and Hack Machine (binary) code : Set D to A-1 Set both A and D to A + 1 Set D to 19 Set both A and D to A + D Set RAM[5034] to D - 1 Set RAM[53] to 171 Add 1 to RAM[7], and store the result in D.

35 Exercise 2 Implement the following high level code snippets using Hack Assembly Language: sum = 0 j = j + 1 q = sum + 12 j Symbol table: j 3012 sum 4500 q 3812 arr (Symbols and values are arbitrary examples) arr[3] = -1 arr[j] = 0 arr[j] = 17 Hack convention: True is represented by -1 False is represented by 0 R13-R15 are temps

36 Exercise 3 Implement the following pseudo code snippets using Hack Assembly Language: goto 50 if (D==0) goto 112 if (D<9) goto 507 Symbol table: sum 2200 x 4000 i 15 END 50 NEXT 120 (All symbols and values are arbitrary examples) if (RAM[12] > 0) goto 50 if (sum>0) goto END Hack convention: True is represented by -1 if (x[i]<=0) goto NEXT False is represented by 0 R13-R15 are temps

Machine (Assembly) Language

Machine (Assembly) Language Machine (Assembly) Language Building a Modern Computer From First Principles www.nand2tetris.org Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Chapter 4: Machine Language

More information

Machine (Assembly) Language Human Thought

Machine (Assembly) Language Human Thought Where we are at: Machine (Assembly) Language Human Thought Abstract design hapters 9, 12 abstract interface H.L. Language & Operating Sys. ompiler hapters 10-11 abstract interface Virtual Machine Software

More information

IWKS 3300: NAND to Tetris Spring John K. Bennett. Assembler

IWKS 3300: NAND to Tetris Spring John K. Bennett. Assembler IWKS 3300: NAND to Tetris Spring 2018 John K. Bennett Assembler Foundations of Global Networked Computing: Building a Modern Computer From First Principles This course is based upon the work of Noam Nisan

More information

Assembler. Building a Modern Computer From First Principles.

Assembler. Building a Modern Computer From First Principles. Assembler Building a Modern Computer From First Principles www.nand2tetris.org Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Chapter 6: Assembler slide 1 Where we are

More information

Computer Architecture

Computer Architecture Computer Architecture Building a Modern Computer From First Principles www.nand2tetris.org Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Chapter 5: Computer Architecture

More information

Assembler Human Thought

Assembler Human Thought Where we are at: Assembler Human Thought Abstract design Chapters 9, 12 H.L. Language & Operating Sys. Compiler Chapters 10-11 Virtual Machine Software hierarchy VM Translator Chapters 7-8 Assembly Language

More information

Chapter 6: The Assembler The Assembler Hack Assembly-to-Binary Translation Specification

Chapter 6: The Assembler The Assembler Hack Assembly-to-Binary Translation Specification Chapter 6: The Assembler 1 1. Introduction Work in progress. 6. The Assembler 1 2. Hack Assembly-to-Binary Translation Specification This section gives a complete specification of the translation between

More information

Chapter 6: Assembler

Chapter 6: Assembler Elements of Computing Systems, Nisan & Schocken, MIT Press, 2005 www.idc.ac.il/tecs Chapter 6: Assembler Usage and Copyright Notice: Copyright 2005 Noam Nisan and Shimon Schocken This presentation contains

More information

STEVEN R. BAGLEY THE ASSEMBLER

STEVEN R. BAGLEY THE ASSEMBLER STEVEN R. BAGLEY THE ASSEMBLER INTRODUCTION Looking at how to build a computer from scratch Started with the NAND gate and worked up Until we can build a CPU Reached the divide between hardware and software

More information

Virtual Machine Where we are at: Part I: Stack Arithmetic. Motivation. Compilation models. direct compilation:... 2-tier compilation:

Virtual Machine Where we are at: Part I: Stack Arithmetic. Motivation. Compilation models. direct compilation:... 2-tier compilation: Where we are at: Virtual Machine Part I: Stack Arithmetic Human Thought Abstract design Chapters 9, 12 H.L. Language & Operating Sys. Compiler Chapters 10-11 Virtual Machine Software hierarchy Translator

More information

4. Computer Architecture 1

4. Computer Architecture 1 Chapter 4: Computer Architecture 1 4. Computer Architecture 1 Make everything as simple as possible, but not simpler. (Albert Einstein, 1879-1955) This chapter is the pinnacle of the "hardware" part of

More information

EC-801 Advanced Computer Architecture

EC-801 Advanced Computer Architecture EC-801 Advanced Computer Architecture Lecture 5 Instruction Set Architecture I Dr Hashim Ali Fall 2018 Department of Computer Science and Engineering HITEC University Taxila!1 Instruction Set Architecture

More information

EP1200 Introduktion till datorsystemteknik Tentamen tisdagen den 3 juni 2014, till 18.00

EP1200 Introduktion till datorsystemteknik Tentamen tisdagen den 3 juni 2014, till 18.00 EP1200 Introduktion till datorsystemteknik Tentamen tisdagen den 3 juni 2014, 14.00 till 18.00 Inga hjälpmedel är tillåtna utom de som följer med tentamenstexten Skriv kurskod, namn och personnummer på

More information

Virtual Machine. Part I: Stack Arithmetic. Building a Modern Computer From First Principles.

Virtual Machine. Part I: Stack Arithmetic. Building a Modern Computer From First Principles. Virtual Machine Part I: Stack Arithmetic Building a Modern Computer From First Principles www.nand2tetris.org Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Chapter 7:

More information

Introduction: From Nand to Tetris

Introduction: From Nand to Tetris Introduction: From Nand to Tetris Building a Modern Computer From First Principles www.nand2tetris.org Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Introduction slide

More information

! Ancient computers. ! Today's microprocessors. Memory. ! Stores data and programs. ! 256 "words." (16 bits each) ! Special word for stdin / stdout.

! Ancient computers. ! Today's microprocessors. Memory. ! Stores data and programs. ! 256 words. (16 bits each) ! Special word for stdin / stdout. What is TOY?. The TOY Machine An imaginary machine similar to:! Ancient computers.! Today's microprocessors. Introduction to Computer Science Sedgewick and Wayne Copyright http://www.cs.princeton.edu/introcs

More information

EP1200 Introduction to Computing Systems Engineering. Computer Architecture

EP1200 Introduction to Computing Systems Engineering. Computer Architecture EP1200 Introduction to omputing Systems Engineering omputer Architecture Perspective on Machine and Assembly Languages Hack is a simple machine language Designed for the simple Hack computer architecture

More information

//converts a string to a non-negative number string2int(string s){

//converts a string to a non-negative number string2int(string s){ EP1200 Introduktion till datorsystemteknik Omtenta fredagen den 22 augusti 2014, 9.00 till 13.00 Possible solutions added with red. Other solutions may of course exist and worth full point. Inga hjälpmedel

More information

Introduction: Hello, World Below

Introduction: Hello, World Below Elements of Computing Systems, Nisan & Schocken, MIT Press, 2005 www.idc.ac.il/tecs Introduction: Hello, World Below Usage and Copyright Notice: Copyright 2005 Noam Nisan and Shimon Schocken This presentation

More information

Lecture 8: Control Structures. Comparing Values. Flags Set by CMP. Example. What can we compare? CMP Examples

Lecture 8: Control Structures. Comparing Values. Flags Set by CMP. Example. What can we compare? CMP Examples Lecture 8: Control Structures CMP Instruction Conditional High Level Logic Structures Comparing Values The CMP instruction performs a comparison between two numbers using an implied subtraction. This means

More information

Computer Architecture

Computer Architecture omputer Architecture Building a Modern omputer From First Principles www.nand2tetris.org Elements of omputing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, hapter 5: omputer Architecture slide

More information

What is TOY? An imaginary machine similar to: ! Ancient computers. ! Today's microprocessors.

What is TOY? An imaginary machine similar to: ! Ancient computers. ! Today's microprocessors. 5. The TOY Machine Introduction to Programming in Java: An Interdisciplinary Approach Robert Sedgewick and Kevin Wayne Copyright 3// 5:3 AM! What is TOY? An imaginary machine similar to:! Ancient computers.!

More information

Assembler. Building a Modern Computer From First Principles.

Assembler. Building a Modern Computer From First Principles. Assembler Buldng a Modern Computer From Frst Prncples www.nand2tetrs.org Elements of Computng Systems, Nsan & Schocken, MIT Press, www.nand2tetrs.org, Chapter 6: Assembler slde Where we are at: Human Thought

More information

Notes: The Marie Simulator

Notes: The Marie Simulator The Accumulator (AC) is the register where calculations are performed. To add two numbers together, a) load the first number into the accumulator with a Load instruction b) Add the second number to the

More information

Chapter 8: Virtual Machine II: Program Control

Chapter 8: Virtual Machine II: Program Control Elements of Computing Systems, Nisan & Schocken, MIT Press, 2005 Chapter 8: Virtual Machine II: Program Control www.idc.ac.il/tecs Usage and Copyright Notice: Copyright 2005 Noam Nisan and Shimon Schocken

More information

Second Part of the Course

Second Part of the Course CSC 2400: Computer Systems Towards the Hardware 1 Second Part of the Course Toward the hardware High-level language (C) assembly language machine language (IA-32) 2 High-Level Language g Make programming

More information

Instruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...

Instruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1... Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,

More information

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs CSC 2400: Computer Systems Towards the Hardware: Machine-Level Representation of Programs Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32)

More information

CS222: Dr. A. Sahu. Indian Institute of Technology Guwahati

CS222: Dr. A. Sahu. Indian Institute of Technology Guwahati CS222: (a) Activation Record of Merge Sort (b) Architecture Space RISC/CISC Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Activation Record in Recursion: Merge

More information

The CPU and Memory. How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram:

The CPU and Memory. How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram: The CPU and Memory How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram: 1 Registers A register is a permanent storage location within

More information

When an instruction is initially read from memory it goes to the Instruction register.

When an instruction is initially read from memory it goes to the Instruction register. CS 320 Ch. 12 Instruction Sets Computer instructions are written in mnemonics. Mnemonics typically have a 1 to 1 correspondence between a mnemonic and the machine code. Mnemonics are the assembly language

More information

Instruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...

Instruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1... Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,

More information

Tutorial 1: Programming Model 1

Tutorial 1: Programming Model 1 Tutorial 1: Programming Model 1 Introduction Objectives At the end of this lab you should be able to: Use the CPU simulator to create basic CPU instructions Use the simulator to execute the basic CPU instructions

More information

Computer Architecture /

Computer Architecture / Computer Architecture 02-201 / 02-601 The Conceptual Architecture of a Computer PC CPU register 0 register 1 register 2 registers hold small amounts of data for processing by the CPU Reading / writing

More information

CSC 8400: Computer Systems. Machine-Level Representation of Programs

CSC 8400: Computer Systems. Machine-Level Representation of Programs CSC 8400: Computer Systems Machine-Level Representation of Programs Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32) 1 Compilation Stages

More information

CS 11 C track: lecture 8

CS 11 C track: lecture 8 CS 11 C track: lecture 8 n Last week: hash tables, C preprocessor n This week: n Other integral types: short, long, unsigned n bitwise operators n switch n "fun" assignment: virtual machine Integral types

More information

8.7 TM: A SIMPLE TARGET MACHINE

8.7 TM: A SIMPLE TARGET MACHINE 8.7 TM: A SIMPLE TARGET MACHINE In the section following this one we will present a code generator for the TINY language. In order to make this a meaningful task, we generate target code directly for a

More information

CS 101, Mock Computer Architecture

CS 101, Mock Computer Architecture CS 101, Mock Computer Architecture Computer organization and architecture refers to the actual hardware used to construct the computer, and the way that the hardware operates both physically and logically

More information

Instruction Sets Ch 9-10

Instruction Sets Ch 9-10 Instruction Sets Ch 9-10 Characteristics Operands Operations Addressing Instruction Formats 1 Instruction Set (käskykanta) Collection of instructions that CPU understands Only interface to CPU from outside

More information

Instruction Set Architecture. "Speaking with the computer"

Instruction Set Architecture. Speaking with the computer Instruction Set Architecture "Speaking with the computer" The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture Digital Design

More information

Instruction Sets Ch 9-10

Instruction Sets Ch 9-10 Instruction Sets Ch 9-10 Characteristics Operands Operations Addressing Instruction Formats 1 Instruction Set (käskykanta) Collection of instructions that CPU understands Only interface to CPU from outside

More information

administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions?

administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions? administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions? exam on Wednesday today s material not on the exam 1 Assembly Assembly is programming

More information

2B 52 AB CA 3E A1 +29 A B C. CS120 Fall 2018 Final Prep and super secret quiz 9

2B 52 AB CA 3E A1 +29 A B C. CS120 Fall 2018 Final Prep and super secret quiz 9 S2 Fall 28 Final Prep and super secret quiz 9 ) onvert 8-bit (2-digit) 2 s complement hex values: 4-29 inary: Hex: x29 2) onvert 8-bit 2 s complement hex to decimal: x3 inary: xe5 Decimal: 58 Note 3*6+

More information

Real instruction set architectures. Part 2: a representative sample

Real instruction set architectures. Part 2: a representative sample Real instruction set architectures Part 2: a representative sample Some historical architectures VAX: Digital s line of midsize computers, dominant in academia in the 70s and 80s Characteristics: Variable-length

More information

Instruction Set. Instruction Sets Ch Instruction Representation. Machine Instruction. Instruction Set Design (5) Operation types

Instruction Set. Instruction Sets Ch Instruction Representation. Machine Instruction. Instruction Set Design (5) Operation types Instruction Sets Ch 10-11 Characteristics Operands Operations Addressing Instruction Formats Instruction Set Collection of instructions that CPU understands Only interface to CPU from outside CPU executes

More information

CHAPTER ASSEMBLY LANGUAGE PROGRAMMING

CHAPTER ASSEMBLY LANGUAGE PROGRAMMING CHAPTER 2 8051 ASSEMBLY LANGUAGE PROGRAMMING Registers Register are used to store information temporarily: A byte of data to be processed An address pointing to the data to be fetched The vast majority

More information

Compiler II: Code Generation Human Thought

Compiler II: Code Generation Human Thought Course map Compiler II: Code Generation Human Thought Abstract design Chapters 9, 12 abstract interface H.L. Language & Operating Sys. Compiler Chapters 1-11 abstract interface Virtual Machine Software

More information

4 Programing Paradigms in 45 Minutes

4 Programing Paradigms in 45 Minutes 4 Programing Paradigms in 45 Minutes Aja Hammerly () Ruby Conf 2017 1 Aja Hammerly http://github.com/thagomizer http://www.thagomizer.com Lawyer Cat Says: Any code is copyright Google and licensed Apache

More information

Programming Model 2 A. Introduction

Programming Model 2 A. Introduction Programming Model 2 A. Introduction Objectives At the end of this lab you should be able to: Use direct and indirect addressing modes of accessing data in memory Create an iterative loop of instructions

More information

SOEN228, Winter Revision 1.2 Date: October 25,

SOEN228, Winter Revision 1.2 Date: October 25, SOEN228, Winter 2003 Revision 1.2 Date: October 25, 2003 1 Contents Flags Mnemonics Basic I/O Exercises Overview of sample programs 2 Flag Register The flag register stores the condition flags that retain

More information

4 Programing Paradigms in 45 Minutes

4 Programing Paradigms in 45 Minutes 4 Programing Paradigms in 45 Minutes Aja Hammerly () RubyHACK 2018 1 Aja Hammerly http://github.com/thagomizer http://www.thagomizer.com Lawyer Cat Says: Any code is copyright Google and licensed Apache

More information

CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART

CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART General Introduction CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART 1) General Introduction (1/5): On Instructions Instruction operate with data or with the flow of the program The following information

More information

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers

More information

The MARIE Architecture

The MARIE Architecture The MARIE Machine Architecture that is Really Intuitive and Easy. We now define the ISA (Instruction Set Architecture) of the MARIE. This forms the functional specifications for the CPU. Basic specifications

More information

Virtual Machine. Part II: Program Control. Building a Modern Computer From First Principles.

Virtual Machine. Part II: Program Control. Building a Modern Computer From First Principles. Virtual Machine Part II: Program Control Building a Modern Computer From First Principles www.nand2tetris.org Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org, Chapter 8:

More information

Building a Virtual Computer

Building a Virtual Computer uilding a Virtual Computer From Gates to Operating System Student Researcher: Elisa Elshamy Faculty Mentor: Dr. Victoria Gitman bstract modern computer can carry a plethora of multifaceted computations.

More information

Lecture A2: X-TOY Programming

Lecture A2: X-TOY Programming Lecture A2: X-TOY Programming What We ve Learned About X-TOY X-TOY: what s in it, how to use it. Bo with switches and lights. 436 bits = 256 6 + 6 6 + 8. von Neumann architecture. Data representation.

More information

CSCI 3130: Formal Languages and Automata Theory Lecture 16 The Chinese University of Hong Kong, Fall 2010

CSCI 3130: Formal Languages and Automata Theory Lecture 16 The Chinese University of Hong Kong, Fall 2010 CSCI 3130: Formal Languages and Automata Theory Lecture 16 The Chinese University of Hong Kong, Fall 2010 Andrej Bogdanov The Church-Turing thesis states that the Turing Machine is as capable as any realistic

More information

Instruction Set II. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 7. Instruction Set. Quiz. What is an Instruction Set?

Instruction Set II. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 7. Instruction Set. Quiz. What is an Instruction Set? COMP 212 Computer Organization & Architecture Quiz COMP 212 Fall 2008 Lecture 7 Fill in your student number only, do NOT write down your name Open book, but NO calculator, NO discussions, Relax and have

More information

Course overview. Introduction to Computer Yung-Yu Chuang. with slides by Nisan & Schocken (

Course overview. Introduction to Computer Yung-Yu Chuang. with slides by Nisan & Schocken ( Course overview Introduction to Computer Yung-Yu Chuang with slides by Nisan & Schocken (www.nand2tetris.org) Logistics Meeting time: 2:20pm-5:20pm, Tuesday Instructor: 莊永裕 Yung-Yu Chuang Webpage: http://www.csie.ntu.edu.tw/~cyy/introcs

More information

Virtual Machine (Part II)

Virtual Machine (Part II) Harvard University CS 101 Fall 2005, Shimon Schocken Virtual Machine (Part II) Elements of Computing Systems 1 Virtual Machine II (Ch. 8) Where we are at: Human Thought Abstract design Chapters 9, 12 H.L.

More information

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control.

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control. Part 5 Intel x86 Jump Instructions Control Logic Fly over code Operations: Program Flow Control Operations: Program Flow Control Unlike high-level languages, processors don't have fancy expressions or

More information

MOS 6502 Architecture

MOS 6502 Architecture MOS 6502 Architecture Lecture 3 Fall 17 1 History Origins lie in the Motorola 6800. Was very expensive for consumers. ($300, or about $1500 in 2017 $s) Chuck Peddle proposes lower-cost, lower-area 6800

More information

COS 140: Foundations of Computer Science

COS 140: Foundations of Computer Science COS 140: Foundations of Computer Science CPU Organization and Assembly Language Fall 2018 CPU 3 Components of the CPU..................................................... 4 Registers................................................................

More information

BASIC COMPUTER ORGANIZATION. Operating System Concepts 8 th Edition

BASIC COMPUTER ORGANIZATION. Operating System Concepts 8 th Edition BASIC COMPUTER ORGANIZATION Silberschatz, Galvin and Gagne 2009 Topics CPU Structure Registers Memory Hierarchy (L1/L2/L3/RAM) Machine Language Assembly Language Running Process 3.2 Silberschatz, Galvin

More information

Computer Architecture 2/26/01 Lecture #

Computer Architecture 2/26/01 Lecture # Computer Architecture 2/26/01 Lecture #9 16.070 On a previous lecture, we discussed the software development process and in particular, the development of a software architecture Recall the output of the

More information

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control.

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control. Part 5 Intel x86 Jump Instructions Control Logic Fly over code Operations: Program Flow Control Operations: Program Flow Control Unlike high-level languages, processors don't have fancy expressions or

More information

IBM PC Hardware CPU 8088, Pentium... ALU (Arithmetic and Logic Unit) Registers. CU (Control Unit) IP.

IBM PC Hardware CPU 8088, Pentium... ALU (Arithmetic and Logic Unit) Registers. CU (Control Unit) IP. IBM PC Hardware CPU 8088, 8086 80286 80386 80486 Pentium... ALU (Arithmetic and Logic Unit) Registers CU (Control Unit) IP Memory ROM BIOS I/O RAM OS Programs Video memory BIOS data Interrupt Vectors Memory

More information

Review: What is a Computer?

Review: What is a Computer? EEC170 Computer Architecture Lecture 2: Instruction Set Architectures October 10, 2005 Soheil Ghiasi Electrical and Computer Engineering University of California, Davis Review: What is a Computer? It has

More information

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access

More information

Course Administration

Course Administration Fall 2018 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture Introduction 4/4 Avinash Karanth Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701

More information

Towards the Hardware"

Towards the Hardware CSC 2400: Computer Systems Towards the Hardware Chapter 2 Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32) 1 High-Level Language Make programming

More information

Program Exploitation Intro

Program Exploitation Intro Program Exploitation Intro x86 Assembly 04//2018 Security 1 Univeristà Ca Foscari, Venezia What is Program Exploitation "Making a program do something unexpected and not planned" The right bugs can be

More information

Computer Architecture

Computer Architecture IWKS 3300: NAND to Tetris Spring 2018 John K. Bennett Computer Architecture Foundations of Global Networked Computing: Building a Modern Computer From First Principles This course is based upon the work

More information

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0

More information

B.V. Patel Institute of Business Management, Computer & Information Technology, Uka Tarsadia University

B.V. Patel Institute of Business Management, Computer & Information Technology, Uka Tarsadia University Unit 1 Programming Language and Overview of C 1. State whether the following statements are true or false. a. Every line in a C program should end with a semicolon. b. In C language lowercase letters are

More information

Motivation. Compiler. Our ultimate goal: Hack code. Jack code (example) Translate high-level programs into executable code. return; } } return

Motivation. Compiler. Our ultimate goal: Hack code. Jack code (example) Translate high-level programs into executable code. return; } } return Motivation Jack code (example) class class Main Main { { static static int int x; x; function function void void main() main() { { Inputs Inputs and and multiplies multiplies two two numbers numbers var

More information

CSC 2400: Computing Systems. X86 Assembly: Function Calls"

CSC 2400: Computing Systems. X86 Assembly: Function Calls CSC 24: Computing Systems X86 Assembly: Function Calls" 1 Lecture Goals! Challenges of supporting functions" Providing information for the called function" Function arguments and local variables" Allowing

More information

CSC 252: Computer Organization Spring 2018: Lecture 11

CSC 252: Computer Organization Spring 2018: Lecture 11 CSC 252: Computer Organization Spring 2018: Lecture 11 Instructor: Yuhao Zhu Department of Computer Science University of Rochester Action Items: Assignment 3 is due March 2, midnight Announcement Programming

More information

Problem with Scanning an Infix Expression

Problem with Scanning an Infix Expression Operator Notation Consider the infix expression (X Y) + (W U), with parentheses added to make the evaluation order perfectly obvious. This is an arithmetic expression written in standard form, called infix

More information

Programmable Machines

Programmable Machines Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational

More information

Computer Science 104:! Y86 & Single Cycle Processor Design!

Computer Science 104:! Y86 & Single Cycle Processor Design! Computer Science 104: Y86 & Single Cycle Processor Design Alvin R. Lebeck Slides based on those from Randy Bryant 1 CS:APP Administrative Homework #4 My office hours today 11:30-12:30 Reading: text 4.3

More information

General issues. Section 9.1. Compiler Construction: Code Generation p. 1/18

General issues. Section 9.1. Compiler Construction: Code Generation p. 1/18 General issues Section 9.1 Target language: absolute machine language all addresses refer to actual addresses program placed in a fixed location in memory relocatable machine language (object modules)

More information

UNIT-II. Part-2: CENTRAL PROCESSING UNIT

UNIT-II. Part-2: CENTRAL PROCESSING UNIT Page1 UNIT-II Part-2: CENTRAL PROCESSING UNIT Stack Organization Instruction Formats Addressing Modes Data Transfer And Manipulation Program Control Reduced Instruction Set Computer (RISC) Introduction:

More information

Lecture 4: MIPS Instruction Set

Lecture 4: MIPS Instruction Set Lecture 4: MIPS Instruction Set No class on Tuesday Today s topic: MIPS instructions Code examples 1 Instruction Set Understanding the language of the hardware is key to understanding the hardware/software

More information

Programmable Machines

Programmable Machines Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational

More information

CS311 Lecture: The Architecture of a Simple Computer

CS311 Lecture: The Architecture of a Simple Computer CS311 Lecture: The Architecture of a Simple Computer Objectives: July 30, 2003 1. To introduce the MARIE architecture developed in Null ch. 4 2. To introduce writing programs in assembly language Materials:

More information

Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College

Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor

More information

LAB 7 Writing Assembly Code

LAB 7 Writing Assembly Code Goals To Do LAB 7 Writing Assembly Code Learn to program a processor at the lowest level. Implement a program that will be used to test your own MIPS processor. Understand different addressing modes of

More information

Computer Architecture

Computer Architecture Computer Architecture Chapter 2 Instructions: Language of the Computer Fall 2005 Department of Computer Science Kent State University Assembly Language Encodes machine instructions using symbols and numbers

More information

Compiler construction. x86 architecture. This lecture. Lecture 6: Code generation for x86. x86: assembly for a real machine.

Compiler construction. x86 architecture. This lecture. Lecture 6: Code generation for x86. x86: assembly for a real machine. This lecture Compiler construction Lecture 6: Code generation for x86 Magnus Myreen Spring 2018 Chalmers University of Technology Gothenburg University x86 architecture s Some x86 instructions From LLVM

More information

Chapter 3 : Control Unit

Chapter 3 : Control Unit 3.1 Control Memory Chapter 3 Control Unit The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional

More information

Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. MIPS Assembly

Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. MIPS Assembly ECPE 170 Jeff Shafer University of the Pacific MIPS Assembly 2 Lab Schedule This Week Activities MIPS discussion Practice problems (whiteboard) Using the QtSPIM simulator Discuss available resources Lab

More information

CS61C Machine Structures. Lecture 13 - MIPS Instruction Representation I. 9/26/2007 John Wawrzynek. www-inst.eecs.berkeley.

CS61C Machine Structures. Lecture 13 - MIPS Instruction Representation I. 9/26/2007 John Wawrzynek. www-inst.eecs.berkeley. CS61C Machine Structures Lecture 13 - MIPS Instruction Representation I 9/26/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L13 MIPS Instruction Representation

More information

Maciej Sobieraj. Lecture 1

Maciej Sobieraj. Lecture 1 Maciej Sobieraj Lecture 1 Outline 1. Introduction to computer programming 2. Advanced flow control and data aggregates Your first program First we need to define our expectations for the program. They

More information

x = 3 * y + 1; // x becomes 3 * y + 1 a = b = 0; // multiple assignment: a and b both get the value 0

x = 3 * y + 1; // x becomes 3 * y + 1 a = b = 0; // multiple assignment: a and b both get the value 0 6 Statements 43 6 Statements The statements of C# do not differ very much from those of other programming languages. In addition to assignments and method calls there are various sorts of selections and

More information

Arithmetic and Bitwise Operations on Binary Data

Arithmetic and Bitwise Operations on Binary Data Arithmetic and Bitwise Operations on Binary Data CSCI 2400: Computer Architecture ECE 3217: Computer Architecture and Organization Instructor: David Ferry Slides adapted from Bryant & O Hallaron s slides

More information

Chapter 11: Compiler II: Code Generation

Chapter 11: Compiler II: Code Generation Elements of Computing Systems, Nisan & Schocken, MIT Press, 2005 Chapter 11: Compiler II: Code Generation www.idc.ac.il/tecs Usage and Copyright Notice: Copyright 2005 Noam Nisan and Shimon Schocken This

More information

378: Machine Organization and Assembly Language

378: Machine Organization and Assembly Language 378: Machine Organization and Assembly Language Spring 2010 Luis Ceze Slides adapted from: UIUC, Luis Ceze, Larry Snyder, Hal Perkins 1 What is computer architecture about? Computer architecture is the

More information