ECE 30 Introduction to Computer Engineering

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1 ECE 30 Introduction to Computer Engineering Study Problems, Set #6 Spring With x = and y = representing two s complement signed integers, perform the following operations, showing all your work. Also verify that your results are correct by converting the numbers into decimal notation. (a) x + y (b) x y (c) x y Solution: (a) x + y x + y = = = ( ) = = We can check our work as follows: x = = ( ) = 2 = y = =

2 Since = , our answer makes sense. (b) x y x y = x + ( y) = ( ) = = = ( ) = = We can check our work as follows: x = = ( ) = 2 = y = = Since = , our answer makes sense. (c) x y Since x is negative, we two-complement x to obtain x, a positive number. We then perform a standard longhand multiplication between the positive numbers x and y. Finally, we negate the result to obtain the correct answer. 2

3 x y = ( x y) = (all zeroes from here on) = (taking 2 s complement) = We can check our work as follows: x = = ( ) = 2 = y = = Since = , our answer makes sense. 2. Bit patterns have no inherent meaning. They may represent signed integers, unsigned integers, floating-point numbers, instructions, and so on. What is represented depends on the context. 3

4 What does the bit pattern represent, assuming that it is (a) a two s complement integer? (b) an unsigned integer? (c) a single precision floating-point number? (d) a MIPS instruction? Solution: (a) = ( ) = = ten (b) = ten (c) sign = 1 exponent = = 90 fraction = = ( 1) 1 ( ) 2 (90 127) = (d) opcode: = sw (so, it must be a I-format instruction) rs: = $t0 rt: = $s0 immediate: = 2 ten So, the instruction is sw $s0, 2($t0). 3. Show the IEEE 754 binary representation for the floating-point number 20 ten in single and double precision. 4

5 Solution: Single Precision Single precision floating point numbers are of the form: ( 1) sign 1.fraction 2 (exponent 127) sign = 0 (20 is positive) exponent = log 2 (20) = 131 = fraction = = 0.25 = 2 2 = So, 20 ten = Double Precision Double precision floating point numbers are of the form: ( 1) sign 1.fraction 2 (exponent 1023) sign = 0 (20 is positive) exponent = log 2 (20) = 1027 = fraction = = 0.25 = 2 2 = So, 20 ten = Write a sequence of MIPS R2000 instructions for computing 0x56789abc 0.75 with the smallest execution time. Assume that 0x56789abc is initially stored in $t0. Use any of the following instructions whose CPI s are as follows: The CPI of mult is 5. The CPI of each of srl, sll, add, and sub is 1. The least significant 32 bits of the resulting product must be stored in $t2. Solution: The instruction sequence is: srl $t2, $t0, 2 # $t2 = multiplicand x 0.25 sub $t2, $t0, $t2 # $t2 = multiplicand x

6 5. Trace the steps of multiplying a 5-bit two s complement multiplicand with a 3-bit two s complement multiplier 111 2, using Booth s algorithm. Assume that the shift-add multiplier shown below is used. Initially, the most significant 5 bits of the 8-bit product register contain and the least significant 3 bits contain the multiplier (111 2 ). When the algorithm completes, the product register must contain the 8-bit product in two s complement representation. Complete the table below. 6

7 Solution: The result of Booth s algorithm is as follows: 7

8 6. Trace the steps of multiplying a 5-bit two s complement multiplicand with a 3-bit two s complement multiplier 011 2, using Booth s algorithm. Assume that the shift-add multiplier shown below is used. Initially, the most significant 5 bits of the 8-bit product register contain and the least significant 3 bits contain the multiplier (011 2 ). When the algorithm completes, the product register must contain the 8-bit product in two s complement representation. Complete the table below. 8

9 Solution: The result of Booth s algorithm is as follows: 9

10 7. We have seen that a subtraction A B can be computed as A + ( B). Assuming that A and B are represented in two s complement representation, construct a 4-bit adder/subtractor using four full adders and XOR gates. The resulting adder/subtractor circuit should perform either addition or subtraction depending on the value of a select bit S. For S = 0, the circuit is to behave as an adder. For S = 1, the circuit is to perform subtraction. Solution: Addition (S = 0): X i = B i and C 0 = S = 0, so the circuit simply adds A and B. Subtraction (S = 1): X i = B i and C 0 = S = 1, so the circuit adds A, B and 1. Since B + 1 generates B in two s complement representation, adding A, B and 1 is equivalent to adding A and B, or, subtracting B from A. 10

11 8. a) Construct a 64-bit, 3-level carry lookahead adder using 4-bit CLA (carry lookahead adder) blocks and 4-bit lookahead carry generator blocks as shown below. b) What is the worst-case propagation delay from a change in inputs to the last sum bit, given the following: - Delay from a i /b i /c 0 to g i /p i (lookahead carry generator inputs inside 4-bit CLA) = 1T. - Delay from g i /p i /c 0 to G/P/c i (lookahead carry generator) = 2T. - Delay from c i to s i (for full adder inside 4-bit CLA) = 1T. Solution: a) A 3-level carry lookahead adder is shown in the diagram below. The P and G outputs from the CLA blocks (indicated with superscript 1) form the p i and g i inputs to the level-2 lookahead carry generator. Each level-2 lookahead carry generator accepts these inputs and generates carries and its own P and G outputs (indicated with superscript 2). This way, the level-2 lookahead carry generators provide the p i and g i inputs to the next level, i.e., the level-3 lookahead carry generator. The level-3 lookahead carry generator generates the carries c 16, c 32, c 48 and c

12 b) The following table provides the sequence of signals generated and the delay involved in generating each of them. Level Signal computed Delay PRE g i, p i inside each 4-bit CLA 1T 1 g i, p i to G 1 and P 1 outputs of 4-bit CLA s 2T 2 G 1 and P 1 to G 2 and P 2 outputs of level-2 lookahead carry generators 2T 3 G 2 and P 2 to c 16, c 32, c 48 outputs of level-3 lookahead carry generator 2T 2 c 16, c 32, c 48 to c 20, c 24, c 28, c 36, c 40, c 44, c 52, c 56, c 60 2T 1 c 20, c 24,..., c 60 to c 21, c 22, c 23, c 25, c 26, c 27,..., c 61, c 62, c 63 2T POST c 21, c 22, c 23, c 25, c 26, c 27,..., c 61, c 62, c 63 to s 21, s 22, s 23, s 25, s 26.s 27,..., s 61, s 62, s 63 1T Therefore, the worst-case delay from the inputs a i /b i /c 0 to the sum bits s i is given by: 1T + 2T + 2T + 2T + 2T + 2T + 1T = 12T. 12

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