Review of instruction set architectures

Transcription

1 Review of instruction set architectures

2 Outline ISA and Assembly Language RISC vs. CISC Instruction Set Definition (MIPS) 2

3 ISA and assembly language Assembly language ISA Machine language 3

4 Assembly language Interface the architecture presents to user, compiler & operating system Low-level instructions that use the datapath & memory to perform basic types of operations arithmetic: add, sub, mul, div logical: and, or, shift data transfer: load, store (un)conditional branches: jump, branch on condition 4

5 Classifying ISAs Five basic dimensions: Operand storage Memory only, memory AND CPU Number of explicit operands per instruction From 0 to N Operand location Operand of ALU instruction also in memory? Operations type Operands size and type 5

6 Basic ISA classes Stack machines (HP3000): Implicit operands (top of stack) Accumulator machines (PDP-8) 1 explicit operand, destination = accumulator Register machines (IBM360) 2/3 explicit operands, destination = register/memory Register-memory Memory-memory Load-store (MIPS) 2/3 explicit operands for ALU instructions 0 memory addresses for ALU instructions Register-register 6

7 Basic ISA classes (2) Example code for the four classes C = A + B 7

8 Evolution of ISA Originally: Architectural decisions made to save hardware Human effort: cheap by comparison Hand-coding was cost effective Not enough memory to run big programs Memory: comparatively cheap Register files expensive Solutions: Accumulator Machines Accumulator and memory 8

9 Eventually: Evolution of ISA (2) Memory got cheaper Bigger software Need for compilers Hardware got cheaper Could do more operations: multiplication, FP, etc. More registers possible Hardware got faster Gap between registers and memories (as today) Solution: Complex Instruction Sets Computers (CISC) Necessary for compilers 9

10 CISC ISA Classical CISC: VAX (Digital) A dominant CISC ISA: x86 (IA-32) 1978: The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The increases address space to 24 bits, +instructions 1985: The extends to 32 bits, new addressing modes : The 486, Pentium, Pentium Pro add a few instructions 1997: MMX is added (Pentium II) 1999: Pentium III (Katmai) more MMX type instructions added Complexity: Instructions from 1 to 17 bytes long Started as 8-bit, grew to 16-bits, wandered around 24 bits one operand must act as both a source and destination one operand can come from memory complex addressing modes 10

11 RISC In the early 80 s a new idea arose: Is it really better to have many complex instructions? Use smaller, regular, fixed-size instruction sets RISC = Reduced Instruction Set Computers Simpler instructions: Compiler can deal more easily with them Easier to optimize execution (parallelism) 11

12 Evolution of ISA: summary Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation High-level Language Based (B ) Concept of a Family (IBM ) General Purpose Register Machines Complex Instruction Sets (Vax, Intel ) Load/Store Architecture (CDC 6600, Cray ) RISC (Mips,Sparc, HP-PA, IBM RS6000, PowerPC ) LIW/ EPIC (IA ) 12

13 RISC ISA Historical reference RISC ISA: MIPS 32 registers 32 bit instruction, fixed format Actually three formats 2 30 memory address space Arithmetic instruction operands must be registers Textbook and examples referred to DLX Based on MIPS ISA 13

14 MIPS ISA Instruction set: Arithmetic/logic add, addi, addu, sub, subi, subu, mult, multu, div, divu, and, or, andi, ori, sll, srl Load/store lw, sw, lb, sb, lui Branches beq, bne, slt, slti, j, jr, jal Instruction format 14

15 MIPS ISA (2) Addressing objects: Big Endian: address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha (Windows NT) 15

16 Why ISA? ISA is important to understand possible architectural optimizations: Pipelining What types of instructions undergo what step? Memory access When and where do I access memory? 16