9/28/2014. CS341: Operating System. Synchronization. High Level Construct: Monitor Classical Problems of Synchronizations FAQ: Mid Semester

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1 CS341: Operating System Lect22: 18 th Sept 2014 Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Synchronization Hardware Support TAS, CAS, TTAS, LL LC, XCHG, Compare, FAI High Level Construct: Monitor Classical Problems of Synchronizations FAQ: Mid Semester Date: 22 nd Sept 2014, Time: 2PM 4PM Venue: L1, L2, L3, L4, (Close Book Exam) Question Pattern : 20% Easy, 40% OK, 40% Tricky/Thinking Proper Mix of Examples, Concepts and Designing Assume that all the instruction are atomic The loadand store machine language instructions are atomic; Thatis,cannotbeinterrupted interrupted We will see: Still we have problem in Synchronization Or some protocol/algorithm to Handle We may need different hardware support, a specific kind of Instruction to be atomic One == (used by )== > other LL+LC==> TAS/CAS/FAI/XCHG==>Lock/Unlock All TAS/CAS/GAS/FAI/XCHG: do the same work Lock/Unlock == > Mutex //Mutexuse L/UL Mutex== > Semaphore // Semaphore uses Mutex Wait() and Signal() Semaphore == > Monitor //Monitor uses Semaphore Many wait/many Signal, Processes in Queue Monitor : Another Abstract Type which use semaphore, mutex, conditions Many systems provide hardware support for Sync. All solutions below based on idea of locking Protecting critical regions via locks Uniprocessors could disable interrupts Currently running code would execute without preemption Generally too inefficient on multiprocessor systems Operating systems using this not broadly scalable 1

2 Multiprocessor disable interrupts Generally too inefficient on multiprocessor systems Operating systems using this not broadly scalable Modern machines provide special atomic hardware instructions Atomic = non interruptible Either test memory word and set value Or swap contents of two memory words Test and Set (TAS) Compare and Swap (CAS) Exchange (XCHG) Fetch and Increment (FAI) How to provide these Load Locked and Store Conditional //Definition: boolean test_and_set(boolean*target) { booleanrv= *target; *target = TRUE; return rv: 1.Executed atomically 2.Returns the original value of passed parameter 3.Set the new value of passed parameter to TRUE. Shared Boolean variable lock, initialized to FALSE Solution: do { while (test_and_set(&lock)) t t(&l ; /* do nothing */ /* critical section */ lock = false; /* remainder section */ while (true); int CAS(int *value, int expected, int new_value){ int temp = *value; if (*value == expected) *value = new_value; return temp; Executed atomically Returns the original value of passed parameter value Set the variable value the value of the passed parameter new_value but only if value == expected. That is, the swap takes place only under this condition. Shared integer lock initialized to 0; do { while (CAS(&lock, 0, 1)!= 0) ; /* do nothing */ /* critical section */ lock = 0; /* remainder section */ while (true); 2

3 Hardware primitive for atomic read+writeis required e.g. Exchange, (XCHG) Test & Set (TAS) // test for unlock (0) then set the lock (1) Fetch& Increment (FAI) Lock: 0 indicates free and 1 indicates locked Code to lock X : r2 = 1 lockit: SPINing Try to test and acquire the lock in a tight loop r2 X //atomic exchange if(r2 0) gotolockit//already locked locks are cached for efficiency, coherence is used in shared multiprocessor A Sahu slide 13 A Sahu 14 Better code to lock X : lockit: r2 =X; // read lock if(r2 0)gotolockit;//notavailable r2 =1; r2 X ; //atomic exchange if(r2 0) gotolockit; //already locked Time LL r1 X // Reading from a location X //do some operation SC r2 X // Storing r2 to location X if unsuccessful r2 ==1 Store will be unsuccessful if values of X is altered/changed by others processor between time of LL and time of SC you have done Load linked/store Conditional A Sahu 15 A Sahu slide 16 lockit: LL r2, X if(r2 0) gotolockit; r2 = 1 ; SCr2, X if(r2==1) gotolockit; A Sahu slide 17 //load locked //not available //storeconditional // store fails redo Spin lock with exponential back off reduces contention Simpler to implement Atomic exchange using LL and SC try: r3 = r2; //move exchange value LL r1, X // load locked SC r3, X //store conditional if(r3==1) gototry ; //store fails redo r2 =r1; //put loaded value in r2 A Sahu slide 18 3

4 Simpler to implement Fetch & increment using LL and SC try: LL r1, X r3 = r1 + 1; SC r3, X if(r3==1) gototry ; //load locked //increment //store conditional //store fails redo A Sahu slide 19 Boolean value Test and set (TAS) Swap truewith current value Return value tells if prior value was trueor false Can reset just by writing false TAS aka getandset public class AtomicBoolean { boolean value; public synchronized boolean getandset(boolean newvalue) { boolean prior = value; value = newvalue; return prior; synchronized function run atomically import java.util.concurrent.atomic; import java.util.concurrent.*; (5) class TASlock { AtomicBoolean state = new AtomicBoolean(false); void lock() { while (state.getandset(true)) { void unlock() { state.set(false); Experiment n threads Increment shared counter 1 million times How long should it take? How long does it take? 4

5 tim me threads TAS lock Ideal What is going on? Lurking stage Wait until lock looks free Spin while read returns true (lock taken) Pouncing state As soon as lock looks available Read returns false (lock free) Call TAS to acquire lock If TAS loses, back to lurking class TTASlock { AtomicBoolean state = new AtomicBoolean(false); void lock() { while (true) { while (state.get()) { if (!state.getandset(true)) return; void lock() { // TASlock while (state.getandset(true)) { tim me threads TAS lock TTAS lock Ideal If the lock looks free But I fail to get it There must be contention Better to back off than to collide again time r 2 d r 1 d d spin lock public class Backoffimplements lock { public void lock() { int delay = MIN_DELAY; while (true) { while (state.get()) { if (!lock.getandset(true)) return; sleep(random() % delay); if (delay < MAX_DELAY) delay = 2 * delay; 5

6 TAS Lock TTAS Lock time Backoff lock threads One == (used by )== > other LL+SC==> TAS/CAS/FAI/XCHG==>Lock/Unlock All TAS/CAS/GAS/FAI/XCHG do the same work Lock/Unlock == > Mutex //Mutexuse L/UL Mutex== > Semaphore // Semaphore uses Mutex Wait() and Signal() Semaphore == > Monitor //Monitor uses Semaphore Many wait/many Signal, Processes in Queue Monitor : Another Abstract Type which use semaphore, mutex, conditions Semaphore: Synchronization tool Provides more sophisticated ways (than Mutex) For process to synchronize their activities. Semaphore: Abstract data type Used for controlling access, by multiple processes Can be access by two atomic Wait()and Signal() EdsgerWybeDijkstra (SSSP Algo) Proberen(to test) Verhogen(to increment) In short P() and V() Semaphore S integer variable Can only be accessed via two indivisible (atomic) operations wait() and signal() Originally called P() and V() Proberen: to_test() Verhogen: to_increment() In short P() and V() voidsynchronized wait(s) { while(s <= 0) ; // busy wait S ; void synchronizedsignal(s) { S++; synchronized function run atomically import java.util.concurrent.atomic; import java.util.concurrent.*; 6

7 Binary semaphore integer value can range only between 0 and 1 Same as a mutexlock Counting semaphore integer value can range over an unrestricted domain Can solve various synchronization problems S=1; // Initialized to 1 // S =0 Locked; S=1 Available voidsynchronized wait(s) { while(s<=0);//busywait wait S ; void synchronizedsignal(s) { S++; S=50;// Initialized to 1 // S =0 Locked; S>=1 Available voidsynchronized wait(s) { while(s <= 0) ; // busy wait S ; void synchronizedsignal(s) { S++; Counting Semaphores : Representation of a limited number of resources If a restaurant has a capacity of 50 people And nobody is there, the semaphore would be initialized edto50 As each person arrives at the restaurant They cause the seating capacity to decrease So the semaphore in turn is decremented. When the maximum capacity is reached The semaphore will be at zero Nobody else will be able to enter the restaurant. Instead the hopeful restaurant goers must wait until someone is done eating. When a patron leaves The semaphore is incremented And the resource becomes available again. Consider P 1 and P 2 that requires 1 to happen before S 2 Create a semaphore synch initialized P1: to 0 P2: S 1 ; signal(synch); wait(synch); S 2 ; Can implement a counting semaphore S as a binary semaphore 7

8 Guarantee that no two processes can execute wait() and signal() on the same semaphore at the same time void synchronized wait(); void synchronized signal(); Implementation becomes the critical section problem where the wait and signal code are placed in the critical section Could now have busy waitingin critical section implementation But implementation code is short Little busy waiting if critical section rarely occupied With each semaphore there is an associated waiting queue Each entry in a waiting queue has two data items: value (of type integer) pointer to next record in the list Two operations: block place the process invoking the operation on the appropriate waiting queue wakeup remove one of processes in the waiting queue and place it in the ready queue wait(semaphore *S){ S >value ; if (S >value < 0) { add this process to S >list; block(); signal(semaphore *S) { S >value++; if (S >value <= 0) { remove a process P from S >list; wakeup(p); typedefstruct{ intvalue; structprocess *list; semaphore; Deadlock two or more processes are waiting indefinitely for an event that can be caused by only one of the waiting processes Let Sand Q be two semaphores initialized to 1 P 0 P 1 wait(s); wait(q); wait(q); wait(s); signal(s); signal(q); signal(q); signal(s); Starvation indefinite blocking A process may never be removed from the semaphore queue in which it is suspended Priority Inversion Scheduling problem when lower priority process holds a lock needed by higher priority process Solved via priority inheritance protocol 8