2.7 Supporting Procedures in hardware. Why procedures or functions? Procedure calls
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1 2.7 Supporting Procedures in hardware Why procedures or functions? Procedure calls Caller: Callee: Proc save registers save more registers set up parameters do function call procedure set up results get results restore more registers restore registers return jal is the only special instruction: the rest is software convention jal = call, jr $ra = return 50 C Functions / Procedures main() { int i, j, k; } i = mult(j, k); int mult (int mcand, int mlier) { int product; } product = 0; while (mlier > 0) { product = product + mcand; mlier = mlier -1; } return product; What information must compiler keep track of? 51
2 Procedure Call Bookkeeping Problems Procedure address Return address Arguments Return value Local variables Register conventions Labels $ra $a0, $a1, $a2, $a3 $v0, $v1 $s0, $s1,, $s7 The caller puts the parameters in $a0-$a3, and uses jal X to jump to procedure X (callee). The callee performs the calculations, places the results in $v0-$v1, and returns control to the caller using jr $ra 52 Procedure Register Use $a0-$a3 (4-7) are used to pass first 4 args to procs. Remaining args are passed on stack $v0-$v1 (2,3) are used to return values from procs $t0-$t9 (8-15, 24, 25) are caller saved regs used to hold temp values that are not saved across proc calls $s0-$s7 (16-23) are callee saved regs used to hold values that are preserved across proc calls $sp (29; stack pointer) points to last location on stack $fp (30; frame pointer) points to first location on stack $ra (31) holds return address for proc call 53
3 Jump and Link Instruction main( ) { s = sum (a, b); } int sum(int x, int y) { return x + y; } Single instruction to jump and save return address jal label: jump and link: save address of next instruction into $ra jump to label 1000 main: add $a0, $s0, $zero # $a0 = a 1004 add $a1, $s1, $zero # $a1 = b 1008 jal sum # $ra = 1012; # jump to sum sum: add $v0,$a0,$a jr $ra # jump to How to read Hex numbers int main (void) { char ch; unsigned int hexdec; ifstream inputfile; } inputfile.open("test.txt"); // open the input file. while (inputfile){ inputfile >> ch; // read the 0 inputfile >> ch; // read the x inputfile >> hex >> hexdec; // read the number. cout << "The hex value is: "; cout<< hex << hexdec<<endl; } 55
4 Convert to Binary void ToBinary(int num) { int i; for(i=31; i > 0; i = i-4){ // Each loop iteration prints 4 bits. cout << ((num >> i) & 1) ; //print msb cout << ((num >> i-1) & 1) ; //print next sb cout << ((num >> i-2) & 1) ; //print next sb cout << ((num >> i-3) & 1) ; //print next sb cout << " " ; //put a space } 56 Review Logical: and, or, andi, ori Shift: sll, srl, sra Multiplication and division: Mult, Div, mfhi, mflo Use special purpose registers (hi, lo) Conditional Jumps beq, bne slt (Set on less than) Combine with beq and bne for >, <, >=, <= Unconditional jumps: j, jr, jal Decision structures If-else, loops (for, while, do-while), case-switch 57
5 Review Procedure call bookkeeping Registers Return address $ra Arguments $a0, $a1, $a2, $a3 Return value $v0, $v1 Caller saved $t0 - $t9 Callee saved $s0 - $s7 Instruction support jal label for procedure call jr $ra for procedure return Communicating with People Data Types Applications / HLL Integer Floating point Character String Date Currency Text Objects double precision Signed, unsigned Hardware support Numeric data types Integers 8 / 16 / 32 / 64 bits Signed or unsigned Binary coded decimal Floating point 32 / 64 /128 bits Nonnumeric data types Characters Strings Boolean (bit maps) Pointers 59
6 MIPS basic data type: 32-bit word A 32-bit word could possible represent Integers (signed or unsigned) 1,128,878,917 Floating point numbers ASCII characters C I S E Memory addresses (pointers) 0x An Instruction 60 Instructions for 16-bit, 8-bit data 16-bit constants (immediates) addi $s0, $s1, 0x8020 lw $t0, 20($s0) Half word (16 bits) lh (lhu): load half word lh $t0, 20($s0) sh: save half word sh $t0, 20($s0) Byte (8 bits) lb (lbu): load byte lb $t0, 20($s0) sb: save byte sb $t0, 20($s0) 61
7 Byte Instructions lb $s1, 4($s0) $s0: $s1: 0x xFFFFFFAA Address 0x Memory Bytes lbu $s1, 2($s0) $s0: $s1: 0x x AA String Manipulation Void strcpy (charx[], char y[]) { } int i; i = 0; while ((x[i]=y[i])!= 0) i = i + 1; C convention: Null byte ( ) represents end of the string Base for x and y are in $a0, $a1, i is in $s0 strcpy: subi $sp, $sp, 4 sw $s0, 0($sp) #save $s0 add $s0, $zero, $zero # i = 0; L1: add $t1, $a1, $s0 lb $t2, 0($t1) # load y[i] add $t3, $a0, $s0 sb $t2, 0($t3) # x[i]=y[i] beq $t2, $zero, L2 # x[i] ==0? addi $s0, $s0, 1 # i = i+1 j L1 L2: lw $s0, 0($sp) addi $sp, $sp, 4 # restore $s0 jr $ra # returen 63
8 2.9 MIPS Addressing Modes Addresses for data and instructions Data (operands and results) Registers Memory locations Constants Instruction PC-relative addressing (branches) Pseudodirect addressing (jumps) 64 Data Addressing Modes Register addressing The most common (fastest and shortest) add $3, $2, $1 Base addressing Operand is at a memory location with offset lw $t0, 20 ($t1) Immediate addressing Operand is a small constant within the instruction addi $t0, $t1, 4 (signed 16-bit integer) 65
9 Instruction Addressing Modes Addresses are 32 bits long Special purpose register PC (program counter) stores the address of the current instruction PC-relative addressing (branches) Address: PC +4 + (constant in the instruction) * 4 beq $t0, $t1, 5 (e.g., 0x ) Pseudodirect addressing (jumps) Address: PC[31:28] : (constant in the instruction) * 4 66 Addressing 1. Immediate addressing op rs rt Immediate 2. Register addressing op rs rt rd... funct Registers Register 3. Base addressing op rs rt Address Memory Register + Byte Halfword Word 4. PC-relative addressing op rs rt Address * 4 Memory PC + Word 5. Pseudodirect addressing op Address * 4 Memory PC Word 67
10 2.16 Alternative ISA PowerPC, SPARC: very similar to MIPS Register: bit registers, Memory: 32-bit address, byte addressable world aligned, only load/store access memory Operations: ALU, load/store, branches/jumps Operands: register, base (memory, lw/sw only), immediate Instructions: three-address architecture, destination first Encoding: 32-bit, 3 types: R, I, J Addressing modes: 3 data + 2 instruction 68 Alternative ISA very structured, no unnecessary baggage Fewer, simpler operations and addressing modes Design Principles: simplicity favors regularity smaller is faster good design demands compromise, make the common case fast Differences from MIPS (tradeoffs: simplicity vs. common case) more addressing modes, some unique instructions (see Appendix D for more) IA-32 (80x86): very different from MIPS 69
11 x86 (IA 32) Milestones 1978: The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The increases address space to 24 bits, +instructions 1985: The extends to 32 bits, new addressing modes : The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: 57 new MMX instructions are added, Pentium II 1999: The Pentium III added another 70 instructions (SSE) 2001: Another 144 instructions (SSE2) 2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64) 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds more media extensions 70 X86 Architecture Two-address architecture The destination is also one of the sources add $s1,$s0 # s0=s0+s1 (C: a += b;) Benefit: smaller instructions smaller code faster Register-memory architecture One operand can be in memory; other operand is register add 12(%gp),%s0 # s0=s0+mem[12+gp] Benefit: fewer instructions smaller code Variable-length instructions (1 to 17 bytes) Small code size (30% smaller) Better instruction cache hit rates Instructions can include 8- or 32-bit immediates 71
12 X86 Features Memory Address space: 16,384 segments (4GB) Little endian 8 32-bit Registers (16-bit 8086 names with e prefix): eax, ecx, edx, ebx, esp, ebp, esi, edi Not general purpose registers Many addressing modes (>10) Data types Signed/unsigned integers (8, 16, and 32 bits) Binary coded decimal integers Floating point (32 and 64 bits) Floating point uses a separate stack 72 X86 Registers Main arithmetic register Pointers (memory addresses) Loops Multiplication and division Pointer to source string Pointer to destination string Base of the current stack frame ($fp) Stack pointer Support for 8088 attempt to address 2 20 bytes using 16-bit addresses Program counter Processor State Word 73
13 X86 Instruction Formats Highly complex and irregular Six variable-length fields Five fields are optional 74 Examples of X86 Instruction Formats 75
14 Integer Instructions Control JNZ, JZ JMP CALL RET LOOP Data Transfer MOV PUSH, POP LES Arithmetic ADD, SUB CMP SHL, SHR, RCR CBW TEST INC, DEC OR, NOR String MOVS LODS 76 Examples of X86 Instructions leal (load effective address) Calculate address like a load, but load address into register Load 32-bit address: leal (%ebp),%esi # esi = ebp Memory Stack is part of instruction set call label (esp-=4; M[esp]=eip+5; eip = label) push places value onto stack, increments esp pop gets value from stack, decrements esp incl, decl (increment, decrement) incl %edx # edx = edx
15 Addressing Modes Encoding Highly irregular, non-orthogonal addressing modes Instruction in 16-bit or 32-bit mode? Not all modes apply to all instructions Not all registers can be used in all modes 78 Addressing Modes Base reg + offset (like MIPS) movl (%ebp), %eax Base reg + index reg (2 regs form addr.) movl (%eax,%ebx),%edi # edi = Mem[ebx + eax] Scaled reg + index (shift one reg by 1,2) movl(%eax,%edx,4),%ebx # ebx = Mem[edx*4 + eax] Scaled reg + index + offset movl 12(%eax,%edx,4),%ebx # ebx = Mem[edx*4 + eax + 12] 79
16 Branch Support Rather than compare registers, x86 uses special 1-bit registers called condition codes that are set as a side-effect of ALU operations S - Sign Bit Z - Zero (result is all 0) C - Carry Out P - Parity: set to 1 if even number of ones in rightmost 8 bits of operation Conditional Branch instructions then use condition flags for all comparisons: <, <=, >, >=, ==,!= 80 While Loop while (save[i]==k) i = i + j; X86 (i,j,k => edx, esi, ebx) leal -400(ebp), eax.loop: cmpl ebx,(eax, edx,4) jne.exit addl esi, edx j.loop.exit: MIPS (i,j,k => $s3, $s4, $s5) Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit add $s3, $s3, $s4 j Loop Exit: 81
17 Current Approach Current technique in P-III, P-IV, Athlon Decode logic translates to MIPS-like uops Execution units run MIPS-like uops Backward compatible Very complex decoder Execution unit has simpler (manageable) control logic, data paths We use MIPS to keep it simple and clean Learn x86 in industry! 82 CISC vs RISC CISC: complex instruction set computer Emphasizes doing more with each instruction Reduces instruction count (IC), Could increase the instruction execution time (CPI) and clock cycle time (CC) RISC: Reduced Instruction Set Computer Reducing the number of complexity of instructions Reduce the instruction execution time and clock cycle time, could increase instruction count Computer performance = IC x CPI x CC Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock rate 83
18 RISC Architecture Design philosophy Only Load-store access memory Fixed-length instructions Three-address architecture Plenty of registers Simple addressing modes Fewer, simpler operations One instruction per cycle Instruction pipelining Let the compiler do it 84 Instruction set architecture a very important abstraction! 85
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