Collapsing for Multiple Output Circuits. Diagnostic and Detection Fault. Raja K. K. R. Sandireddy. Dept. Of Electrical and Computer Engineering,

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1 Diagnostic and Detection Fault Collapsing for Multiple Output Circuits Raja K. K. R. Sandireddy Dept. Of Electrical and Computer Engineering, Auburn University, Auburn AL USA

2 Outline Introduction Background Equivalence & Dominance Functional collapsing Equivalence & Dominance definitions Algorithm to find dominance relations Results Application Conclusions & Future work. Nov, 24 VLSI Design & Test Seminar 2

3 Introduction Test Vector Generation Flow DUT Fault Model Generate fault list Collapse fault list Required Fault Coverage Generate test vectors Nov, 24 VLSI Design & Test Seminar 3

4 Stuck-at fault Single stuck-at fault model is the most popular model. a a c c a c b b b Subscript fault notation: a implies stuck-at on the line a Nov, 24 VLSI Design & Test Seminar 4

5 Equivalence Structural R-equivalence : Two faults f and f 2 are said to be R-equivalent if they produce the same reduced circuit graph when faulty values are implied and constant edges are removed. Functional F-equivalence : Two faults f and f 2 are said to be F-equivalent if they modify the boolean function of the circuit in the same way, i.e. they yield the same output functions. E. J. McCluskey and F. W. Clegg, Fault Equivalence in Combinational Logic Networks, IEEE Trans. On Computers, vol. C-2, No., Nov 97, pp Nov, 24 VLSI Design & Test Seminar 5

6 Equivalence a a c c a = b = c : Equivalence b b Equivalent faults are indistinguishable. Nov, 24 VLSI Design & Test Seminar 6

7 Dominance If all the tests of a fault f detect another fault f 2, then f 2 is said to dominate f. a a a = b = c : Equivalence c c a c : Dominance b c : Dominance b b Nov, 24 VLSI Design & Test Seminar 7

8 Fault Collapsing Equivalence Collapsing: It is the process of selecting one fault from each of the equivalence sets Dominance Collapsing: After equivalence collapsing, the dominating fault is left out retaining the dominated fault. For the OR gate, Equivalence collapsed set = {a, b, c, c } Dominance collapsed set = {a, b, c } a a c c b b Nov, 24 VLSI Design & Test Seminar 8

9 Collapse Ratio Collapse Ratio = Set of Collapsed Faults Set of all Faults Example: Full adder circuit. Total faults: 6 Structural equivalent collapsed set 2, 3 = 38 (.63) Structural dominance collapsed set 3 = 3 (.5) 2 Using Hitec. 3 Using Fastest. Nov, 24 VLSI Design & Test Seminar 9

10 Dominance Graph A 2-input OR gate and its dominance graph a b c a b c c a b Connectivity Matrix a a b b c c a a b b c c Used for fault collapsing. Nov, 24 VLSI Design & Test Seminar

11 Functional Equivalence F F Z F If faults in blocks F and F 2 are 2 equivalent, then Z = F Z F 2 For the full-adder, functional equivalence collapsed set = 26 (.43) {Structural equiv. = 38, Structural dom. = 3} Nov, 24 VLSI Design & Test Seminar

12 Functional Dominance 4 F F Z F 2 If the fault introduced in block F dominates the fault in block F 2, then Z is always. For the full adder, functional dominance collapsed set = 2 (.2) {Structural equiv. = 38, Structural dom. = 3, Functional equiv.= 23} 4 V. D. Agrawal, A. V. S. S. Prasad and M. V. Atre, Fault Collapsing via Functional Dominance, Proc. International Test Conf. 23, pp Nov, 24 VLSI Design & Test Seminar 2

13 Equivalence Definitions Fault Equivalence: Two faults are equivalent if and only if the corresponding faulty circuits have identical output functions. For multiple output circuits, there are two definitions of equivalence. Diagnostic equivalence - Two faults of a Boolean circuit are called equivalent if and only if the pair of the output functions is identical at each output of the circuit. Detection equivalence - Two faults are called detection equivalent if and only if all the tests that detect one fault also detect the other fault, not necessarily at the same output. For single output circuits, diagnostic & detection equivalence mean the same. Diagnostic equivalence implies detection equivalence. Nov, 24 VLSI Design & Test Seminar 3

14 Example to demonstrate Detection Equivalence s-a- Q P s-a- s-a- R A B s-a- Y The faults c and Y are detection equivalent faults. c s-a- Z For the full adder, detection equivalence collapsed set = 23 (.38) {Structural equiv. = 38, Structural dom. = 3, Functional equiv.= 26, Functional dom.= 2} Nov, 24 VLSI Design & Test Seminar 4

15 Dominance Definitions Diagnostic dominance - If all the tests of a fault f detect another fault f 2 on the exact same outputs where f was detected, then f 2 is said to dominate f. Detection dominance - If all the tests of a fault f detect another fault f 2, irrespective of the output where f was detected, then f 2 is said to detection dominate f. Diagnostic dominance implies detection dominance. For the full adder, detection dominance collapsed set = 6 (.) {Structural equiv. = 38, Structural dom. = 3, Functional equiv.= 26, Functional dom.= 2, Detection equiv.= 23} Nov, 24 VLSI Design & Test Seminar 5

16 Functional Dominance Faults in this circuit are checked for redundancy F D or D F D or D F Fault introduced in this circuit Nov, 24 VLSI Design & Test Seminar 6

17 Algorithm to find all dominance relations.. Select a fault from the given circuit and build the circuit as shown in previous slide with the fault introduced in the bottom block whose function is F. 2. Check for redundant faults in the top block, F. 3. For each redundant fault found in step 2, a is placed in the connectivity matrix at the intersection of the row corresponding to the redundant fault and the column corresponding to the fault in the bottom block. Thus, we obtain all values of a column of the connectivity matrix in a single iteration. 4. Go to step until there is no fault left. 5. At the end of the algorithm, we will get the connectivity matrix of the dominance graph with all the functional dominance relations included. Nov, 24 VLSI Design & Test Seminar 7

18 Algorithm contd. Then, the connectivity matrix is examined and the faults that are not dominated by any other faults are considered in the collapsed set. This step is same as Algorithm Equivalence and Algorithm Dominance as from the paper by Prasad, et al. 5 If we just do Algorithm Equivalence, we will have equivalence collapsing results. For simplicity, the redundant faults of the given circuit (standalone F ) are not considered in step. 5 A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets, Proc. International Test Conf., Oct 22, pp Nov, 24 VLSI Design & Test Seminar 8

19 For multiple output circuits F F F F F F Diagnostic collapsing Detection collapsing Nov, 24 VLSI Design & Test Seminar 9

20 Results: Collapsing 2 Using Hitec 3 Using Fastest 4 Agrawal, et al. ITC 3 Nov, 24 VLSI Design & Test Seminar 2

21 Results: Test Vectors Test vectors obtained using Fastest ATPG 3. No. of test vectors (no. of target faults) Circuit Equiv. Structural Dom. Functional New Results Diagnostic Dominance Detection Dominance XOR 4 (6) 4 (3) 4 (4) 4 (4) Full Adder 6 (38) 6 (3) 5 (2) 5 (6) 8-bit Adder 3 (29) 2 (226) 3 (96) 4 (56) ALU 37 (293) 35 (24) 39 (47) 29 (84) 3 T. P. Kelsey, K. K. Saluja and S. Y. Lee, An efficient Algorithm for Sequential Circuit Test Generation, IEEE Trans. Computers, vol. 42, no., Nov. 993, pp Nov, 24 VLSI Design & Test Seminar 2

22 Application Hierarchical fault collapsing: Create a library For smaller sub-circuits, use the exhaustive collapsing using the method discussed. For larger sub-circuits, use the structural collapsing. At the top level, do the structural collapsing using the library information to collapse the faults at lower levels. Detection collapsing can be used only for those subcircuits whose outputs are POs at the top-level. Nov, 24 VLSI Design & Test Seminar 22

23 Hierarchical fault collapsing Comparison of fault collapse ratios of adders Total Faults: Full adder: 6, 8-bit Adder: 466, 32-bit Adder: 858, 64-bit Adder: 374. Full Adder 8-bit Adder 32-bit Adder 64-bit Adder Structural Equiv. Detection Equiv. Structural Dom. Detection Dom. Nov, 24 VLSI Design & Test Seminar 23

24 Conclusions Use the techniques described with hierarchical fault collapsing. Collapse ratios using detection dominance collapsing is about -2%. Reduction of the test vectors. Reduction in the fault simulation effort. Use caution when using dominance collapsing!! Nov, 24 VLSI Design & Test Seminar 24

25 Future Work Implementation using hierarchical collapsing. Efficient redundancy detection program. Customized ATPG to obtain minimal test vector set. Nov, 24 VLSI Design & Test Seminar 25

26 THANK YOU Nov, 24 VLSI Design & Test Seminar 26