University of Illinois at Chicago. Lecture Notes # 13

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1 1 ECE 366 Computer Architecture Instructor: Shantanu Dutt Department of Electrical and Computer Engineering University of Illinois at Chicago Lecture Notes # 13 COMPUTER ARITHMETIC: Iterative Division Techniques c Shantanu Dutt, UIC 1

2 and an integer remainder Integer FP division: Given 2 integers the dividend and the divisor, Integer division: Given 2 integers want to obtain an integer quotient the dividend and the divisor, we, s.t. Binary division is much simpler, since the next quotient bit is either a 0 or 1 depending on whether the partial remainder is less than or greater than/equal to the divisor, respectively Radix division is essentially a trial-and-error process, in which the next quotient bit is chosen from Example: Division Basics 2

3 s.t. c Shantanu Dutt, UIC 3 We will talk about division of unsigned numbers first we want to obtain a floating-point (FP) or real quotient 3

4 4 Division SHR-Divisor Method Start subtraction offrom left most position of; SHR for next subtraction every iteration Pencil-paper division example: c Shantanu Dutt, UIC 4

5 5 Division SHL-Partial-Remainder Method Instead of shifting the divisor right by 1 bit, the partial remainder can be shifted left by one bit Example: c Shantanu Dutt, UIC 5

6 -bit subtractions to c Shantanu Dutt, UIC 6 Note that is stored as a 4-bit # (0010) in the computer. The type of manual adjustment done in the above example of converting 4-bit subtractions into 2-bit ones (in general, -bit ones, where) is not possible in a computer Another Example: Some higher order bits of the -bit divisor are 0s: Division Handling with 0 s in High-Order Bits 6

7 c Shantanu Dutt, UIC 7 Method 1: Shift to the left by division for steps for an integer Example: bits (until its MSB is a 1), do the (more steps for a FP ) Two ways to tackle the problem: Problem with having higher order bits as 0s: Division Handling with 0 s in High-Order Bits (contd.) 7

8 Method 2: Augment 8 Division Handling with 0 s in High-Order Bits (contd.) Problem with having higher order bits as 0s: to the left by division for steps for an integer Example: bits that are all 0s. Perform more steps for a FP and This is the type of division algorithm used in a computer c Shantanu Dutt, UIC 8

9 are both 1s but Thus need an extra bit in AC is to catch a 1 out of AC when the MSBs of the partial remainder and Example for needing an extra bit to the left of the dividend to catch a 1 on a shift left (required when originally has more bits than (e.g., dividing an 8-bit number by a 6-bit one): Division A Caveat 9

10 added later to of bits to start with (this does not count the c Shantanu Dutt, UIC 10 ). number bits that are The adder/subtracter thus also needs to be bits; see block diagram of divider given next. NOTE: The extra bit is never required when both and have the same 10

11 and ) 1. To compute, store in the register, in the register and 0 in AC (Accumulator), and 0 in(holds the quotient bit before the shift left). Note that is an-bit register, while are -bit ones, with 0 s initially in their th bits. Repeat the following steps times: 2. Shift AC-Q-T register combination left 1 bit (initially, this has the effect of adding on 0s to the left of the dividend) 3. Perform (subtract divisor from -bit partial remainder Serial division for 16 bit unsigned numbers 17 From Control Unit C out 17 bit Add/Sub 1 1 Accumulator Q M XOR 17 Dividend D T Divisor V From Control Unit Simple restoring division algorithm: Division Complete Algorithm # 1 11

12 4. If the result is negative, set c Shantanu Dutt, UIC 12 NOTE: Notice similarity between hardware for A&S multiplication and division. The same hardware with additional control can be used for both purposes., otherwise set 5. If the result of step 2 is negative, restore the old value of AC by doing 12

13 else perform This works because: Let of the th iteration. After a SHL and subtraction, is computed. In restoring division: If this result ( ) is -ve, restoration and then another subtraction in the next iteration gives us. be the contents of register AC-Q at the beginning 4. If the result is negative, set, otherwise set Repeat the following steps times: 2. Shift AC-Q-T register combination left 1 bit 3. If current Q[0] is 0 and this is not the 1st iteration then perform 1. Same initialization as before. Non-restoring division algorithm: An extra addition step is needed in the previous algorithm to restore the old value of when the result of a subtraction is negative. This step is eliminated in non-restoring division: Division Complete Algorithm # 2 13

14 In non-restoring division: If the result of the previous iteration ( c Shantanu Dutt, UIC 14 bit of the quotient. Thus non-restoring division will give us the same quotient as restoring division, though faster. Thus non-restoring division works correctly since restoring division is correct. -ve, we do not restore but in the th iteration we perform a SHL to get and then add to get. This gives us the same result in AC-Q as in restoring division, and based on this same result we determine the next ) is 14

15 15 Two s Complement Division (contd.) There are no simple division algorithms for 2 s complement #s unlike the case for multiplication This is primarily due to the difficulty in selecting the quotient bits in such a way that it has tthe correct +ve or -ve 2 s complement representation Thus the approach generally followed is to negate a -veor, perform division and then negate the quotient if only one ofor was -ve A more efficient division algorithm for 2 s complement #s is the SRT method (for Sweeney, Robertson and Tocher, its inventors); see Ref. text # 1 (Hennesey and Patterson) for this algorithm if interested c Shantanu Dutt, UIC 15

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