Newton-Raphson division module via truncated multipliers

Transcription

1 Newton-Raphson dvson module va truncated multplers Alexandar Tzakov Department of Electrcal and Computer Engneerng Illnos Insttute of Technology Chcago,IL 60616, USA Abstract Reducton n area and power dsspaton of Newton-Raphson (N-R) dvson module could be acheved by substtutng the standard parallel multpler wth truncated multpler. Ths s possble snce when standard multplers are employed, ther products are rounded to avod unnecessary growth n word sze. Truncated array multplers, on the other hand, wll generate a hgher maxmum absolute error, and even when lmted to one unt n the last place t s not clear how t wll affect the performance of the unt. In ths paper error analyss of 8 -bt N-R module, usng Varable Correcton Truncated Array and Constant Correcton Truncated Dadda multplers s performed. The maxmum and absolute errors are analyzed and contrasted from the mplementatons of the standard multplers. I.Introducton Typcally dvson n Dgtal Sgnal Processng (DSP) Processors s mplemented ether wth multplcatve algorthms such as Newton-Raphson (N-R) and Goldschmdt's algorthms, or va addtve algorthms such as dgt-recurrence methods [1] and SRT dvson. If the N-R method s chosen, the usage of parallel multpler s nevtable. Parallel multplers can consume a good porton of the Processor area, and therefore t s desred to develop technques to mnmze ther sze. One such technque s the employment of truncated multplers [3], whch s especally sutable when N-R dvson s used, snce the product of the multplcaton s rounded to avod unnecessary growth n the word sze. Unfortunately truncated multplers wll ntroduce addtonal error, and even when ther mplementaton allows, to lmt the error to the Last Sgnfcant Bt and N-R approxmaton s Quadratcally convergent, Error Analyses on the dvson should be performed to determne the accuracy of the processor. In ths paper Error Analyss of 8-bt N-R Module s perfumed for standard and truncated, Dadda and Array, multpler mplementatons. Secton gves an overvew of N-R dvson and truncated multplers, Secton 3 present the mplementaton and data, and Secton 4 provdes the concluson.

2 .0. Newton-Raphson dvson [] II. Prevous Research.0.1. Modfed Newton-Raphson dvson The Newton-Raphson dvson algorthm provdes a hgh-speed method for performng dvson usng multplcaton and subtracton. Computng the recprocal s the bass of ths method sometmes called multplcatve-dvde system, snce dvson s performed va multplcaton. The algorthm computes the quotent usng three steps: 1. Obtan an ntal recprocal approxmaton, 1 0 D. Perform an teratve mprovement of the recprocal approxmaton (k tmes): + 1 = ( D ) Perform fnal multplcaton to obtan the product: Q = A The remnder can be computed usng hgher precson arthmetc as: R = A Q D Newton-Raphson teraton s used to mprove the approxmaton 1/ D. Newton-Raphson teratons fnds the zero of a functon f ( ) by usng the followng teraton equaton: f ( ) + 1 = f ' ( ) Where s an ntal approxmaton to the root of the functon and + 1 s the mprovent to the ntal approxmaton To approxmate 1/ Dt s necessary to chose a functon that s zero for = 1/ D f ( ) = D 1/ f '( ) = 1/

3 Pluggng these value nto the Newton-Raphson teratve equaton gves + 1 = = = = = D 1/ D f ( ) = f '( ) D ( D = + ) = = Table 1 gves an example of Newton-Raphson dvson teratons for D=0.65, N=0.875 and ntal approxmaton = 1. 0 D D After the fnal teraton the quotent can be computed as Q = A 4 = = Error analyses of Modfed Newton-Raphson dvson Error analyses should always be performed on any algorthm before mplementaton. The absolute error n the approxmaton 1/ D s ε 1 = 1/ D = 1/ D + ε 1 Replacng by 1/ D ε , n the Newton-Raphson dvson equaton gves. = *( D * ) = = (1/ D + ε = (1/ D + ε 1 1 = 1/ D D * ε ) * ( D * (1/ D + ε ) * (1 D * ε 1 1 ) = 1 )) =

4 Therefore the absolute error decreases quadratcally as: ε = D ε * Modfed Newton-Raphson dvson Implementaton To ease hardware mplementaton, the Newton-Raphson teraton equatons can be rewrtten as: V = 1 * Y Y + 1 = Y + Y * V Where, s the dvdend, s the number of the approxmaton, Y s ntal (=0) or prevous (I>0) approxmaton and V s the teraton correcton..1. Truncated Array Multplers [3][7] Truncated multplcaton s a technque used to conserve multpler area when the full precson of the multplcaton s not requred [3][5][6]. Usng ths technque, several of the least sgnfcant columns of the orgnal multpler are elmnated and correcton terms are added to the result to reduce the overall error. By properly selectng the number of columns and the correcton terms, the error can be made small enough to meet the requrements of a gven applcaton or system. In the followng dscusson, t s assumed that an unsgned n-bt multplcand A s multpled by an unsgned n-bt multpler B to produce an unsgned n-bt product P. For fractonal numbers, the values for A, B, and P are n 1 n n+ A = a 1 n n+ B = b 1 P = p = 0 = 0 = 0 n+ The multplcaton matrx for P = A * B s shown n Fg.1.A. For most hghspeed applcatons, parallel multplers are used to produce the product. In many computer systems, the n-bt products produced by the parallel multplers are rounded to n bts to avod growth n word sze. As presented n [8] - [11], truncated multplcaton provdes an effcent method for reducng the hardware requrements of rounded parallel multplers. Wth truncated multplcaton, only the n + k most sgnfcant columns of the multplcaton matrx are used to compute the product. The error produced by omttng the n - k least sgnfcant columns and roundng the fnal result to n bts s estmated, and ths estmate s added wth the n +k most sgnfcant columns to produce the rounded product. Although ths leads to addtonal error n the rounded product, varous technques have been developed to help lmt ths error.

5 Fg.1.A Standard Multplcaton Matrx.1.1. Constant Correcton Truncated Multplers Wth the Constant Correcton Truncated Multpler presented n [9], a constant s added to columns n - 1 to n - k of the multplcaton matrx. The constant helps compensate for the error ntroduced by omttng the n - k least sgnfcant columns (called reducton error), and the error due to roundng the product to n bts (called roundng error). The expected value of the sum of ths error ETOTALs computed by assumng that each bt n A, B and P has an equal probablty of beng one or zero. As descrbed n [9], ths gves n k 1 E TOTAL = 0.5 ( + 1) = 0 n+ n 1 (1 k ) The constant CTOTALs obtaned by roundng - E TOTAL to n+k fractonal bts, such that Round( n+ k C TOTAL = n+ k E TOTAL where Round(x) ndcates that x s rounded to the nearest nteger. The multplcaton matrx for a truncated multpler that uses ths method s shown n Fgure.1.1.A. )

6 Fg.1.1.A Constant Correcton Truncated Multplcaton Matrx Constant Correcton Truncated Multplers Implementaton Tree multplers can be effcently mplemented usng the Constant Correcton Truncated Multpler method. The hardware saved wth truncated Dadda tree multplers s t(t + 1)/ AND gates and (t - 1)(t - )/ full adders. The number of half adders saved s between 1 and t, and depends on the values of n and k. The sze of the carry-propagate adder s reduced by (t - 1)-bts, and the k least sgnfcant adders n the carry-propagate adder do not need to produce sum bts. To add the correcton constant, m of the half adders are changed to specalzed half adders, where m corresponds to the number of ones n C TOTAL. Fg A shows the dot dagram of an 8 by 8 truncated Dadda multpler, whch uses the Constant Correcton Truncated Multplcaton method [9]. For ths multpler, n = 8 and k = 3,so the t = 5 least sgnfcant columns of the dot dagram are elmnated. The correcton 8 constant C = 0.65 * s added by changng the two-crcled half adders TOTAL to specalzed half adders. Ths multpler has a maxmum absolute error of 8 approxmately0.754 *. Compared to a standard 8 by 8 Dadda multpler, ths multpler requres 15 fewer AND gates, 6 fewer full adders, fewer half adders, and 4 fewer bts n the carry-propagate adder.

7 (a) Standard Dadda Tree Multpler (b)truncated Dadda Tree Multpler Fg A 8x8 Dadda Tree Multpler.1.. Varable Correcton Truncated Multplers In [11], the Varable Correcton Truncated Multpler s ntroduced. Wth ths type of multpler,the values of the partal product bts n column n _ k _ 1 are used to estmate the error due to leavng of the n-k least sgnfcant columns. Ths s accomplshed by addng the partal products bts n column n - k - 1 to column n - k. To compensate for the roundng error that occurs when truncatng the products bts n columns n - 1 to n - k, a roundng constant, C ROUND, s added to the multplcaton matrx. Snce each product bt has an equal probablty of beng one or zero and the roundng constant cannot go beyond column n _ k, the value used for C ROUND s C ROUND = k n 1 1 (1 + )

8 whch corresponds to the addtve nverse of the expected value of the roundng error, truncated after column n-k. The correcton constant s added by puttng ones n columns n- to n-k, as shown n Fg.1..A. Compared to Constant Correcton Truncated Multplers, Varable Correcton Truncated Mult-plers have less average, mean square and maxmum error for gven values of n and k, but requre more hardware. Fg.1..A Varable Correcton Multpler Matrx.1.1. Varable Correcton Truncated Multplers Implementaton As dscussed n [7], array multplers can be mplemented more effcently as Varable Correcton Truncated Multplers. Fgure.1.1..A shows the block dagram of a standard 8 by 8 array multpler. The cells along each dagonal n the array multpler correspond to a column n the multplcaton matrx. In ths dagram, a modfed half adder (MHA) cell conssts of an AND gate and a half adder. The AND gate generates a partal product bt, and the half adder adds the generated partal product bt and a partal product bt from the prevous row to produce a sum bt and a carry bt. Smlarly, a modfed full adder (MFA) conssts of an AND gate, whch generates a partal product bt, and a full adder whch adds the partal product bt and the sum and carry bts from the prevous row. The bottom row of adders produces the most

9 sgnfcant half of the product. To mprove performance, ths row of adders s sometmes replaced by a fast n-bt carry-propagate adder. An n by n array multpler requres n^ AND gates, n half adders, and n^-n full adders. Fg.1.1..A 8x8 Standard Array Multpler The Varable Correcton Truncated Multplcaton method provdes an effcent method for reducng the power dsspaton and hardware requrements of rounded array multplers. Wth ths method, the dagonals that produce the t = n - k least sgnfcant product bts are elmnated. To compensate for ths, the AND gates that generate the partal products for column t - 1 are used as nputs to the modfed adders n column t. Snce the k remanng modfed full adders on the rght-hand-sde of the array do not need to produce product bts, they are replaced by modfed reduced full adders (RFAs), whch produce a carry, but do not produce a sum. To add the constant that corrects for roundng error, k - 1 of the MHAs n the second row of the array are changed to modfed specalzed half adders (SHAs). SHAs are equvalent to MFAs that have an nput set to one [1]. Array multplers that use ths method requre t(t -1)/ fewer AND gates, (t-1)(t-

10 )/ fewer full adders, and (t-1) fewer half adders than standard array multplers [11]. Fgure Fg.1.1..B shows the block dagram of a 8 by 8 array multpler that uses the Varable Correcton Truncated Multplcaton method. For ths multpler, n=8, k=, and t=6, whch results n a hardware savngs of 15 AND gates, 10 full adders, and 5 half adders. The two MFAs on the rght-hand-sde of 8 the array are replaced by RFAs. The roundng correcton onstant C ROUND = 0.5 *, s added by changng one of the MHAs n the second row to a SHA. For ths 8 example, only one MHA s modfed snce C = 0.5 * has a sngle '1'. Ths ROUND 8 multpler has a maxmum absolute error of approxmately 0.73 *. In comparson, an 8 by 8 rounded multpler has a maxmum absolute error 8 of0.5*. Fg.1.1..B 8x8 Truncated Array Multpler

11 III. Results 3.1. Implementaton Overvew The mplementaton was completed based on an 8-bt word sde. Bt representaton chosen was s complment fxed-pont fractons whch effectvely sets the doman n decmal representaton of [-; 1,984375]. The N-R Module block dagram s presented n Fg 3.1.A. Ths module computes the value of D=A/B. The computaton s completed n 6+1 clock cycles (6 = 3 teratons * clock cycles, and 1 clock cycle for the fnal result). For ths mplementaton no lookup tables were employed for the ntal approxmaton, nstead 0.75 of 0.75 were chosen based on the sgn of B. The dfference between the mplementaton wth truncated vs. standard multpler have been that wth standard multplers the product has been rounded from 16 to 8 bts, where wth truncated multpler t has been truncated from 10 to the desred 8 bts. Prev. Approxmaton Intal Aproxmaton CTRL3 SEL MU x1 OUT A D (0.75) (-0.75) V A B CTRL0 A D SEL MU x1 OUT CTRL1 A SEL B C MU 3x1 OUT Op1 Op A MULTIPLIER P B CTRL1 A D SELMU x1 OUT Product 16 / Product 10 IN ROUNDER / TRUNCATER OUT PRODUCT 8 Product 8 In 1's Complment Out 0 Cn A FA Z B In PLUS 1 Out Load0 Load Q Regster D (Y) REGISTER (Prev. Approxmaton) Load1 Fnal Result Load Fg 3.1.A N-R Module block dagram Q Regster D V1 REGISTER

12 Pearl scrpts have been used to generate Verlog netlsts for the multplers. The truncated tree multplers (Dadda), use constant correcton method and wll be called for smplcty D-CCT, on the other hand the truncated array multpler uses varable correcton method and wll be called for smplcty A- VCT. For synthess Cadance s Slcon Ensemble have been used, wth IIT 0.5 mcron Standard Cell Lbrary. In addton a C program has been developed for statstcal analyses on the results. 3.. Result. The man goal of ths paper was to estmate the maxmum absolute error of the N-R module wth standard multpler and to contrast t wth that of truncated mplementaton. For that reason exhaustve test of the unt has been performed wthn the operatonal range that s shown n Table 3.1. Table 3.1 Postve/Negatve Range of A Range of B Postve [0.5 ; ] [ ; ] Negatve [- ; ] [ ; ] The exhaustve test conssted of a total of 4,769 test vectors for each mplementaton, whch ran true smulaton of the Verlog code. All of the 4 outputs were then analyzed wth the customzed C program, n order to determne maxmum and relatve bt and decmal errors. All the errors were determned n terms of the best result n the gven bt representaton, ths requred software emulaton of the dvson n the C code. Table 3..1 represents the statstcal data for the Standard Array vs. A-VCT, and Table 3.. provdes the same data for Standard Dadda vs. D-CCT.. Synthess has been performed to verfy the exact amount of area reductons of the N-R Module due to usage of truncated multplers. The data s presented n table 3.3; agan the focus was on comparsons between the standard and truncated mplementatons. Table 3.3 Area /In Grd Square Unts/ Area /In Grd Square Unts/ Standard Array A-VCT Rato Standard Dadda D-CCT

13 Table 3..1 Standard Vs. Truncated Array (Maxmum Absolute and Relatve Errors) Implementatons Maxmum Absolute Bt Error Maxmum Absolute Dec. Error At least one Case /The error can be reached n multple cases/ Standard nd LSB % A(Bt)= A(Dec)= B(Bt)= B(Dec)= Relatve Error % Generated Result(Dec)= Expected Result(Dec)= Truncated 3 th LSB %= A(Bt)= A(Dec)= % B(Bt)= B(Dec)= Generated Result(Dec)= Expected Result(Dec)= Table 3..1 Standard Vs. Truncated Dadda (Maxmum Absolute and Relatve Errors) Implementatons Maxmum Absolute Bt Error Maxmum Absolute Dec. Error At least one Case /The error can be reached n multple cases/ Standard nd LSB % A(Bt)= A(Dec)= B(Bt)= B(Dec)= Relatve Error % Generated Result(Dec)= Expected Result(Dec)= Truncated nd LSB %= A(Bt)= A(Dec)= % B(Bt)= B(Dec)= Generated Result(Dec)= Expected Result(Dec)=

14 3.3. Analyss of the Result. For the Array multplers, as the results of the truncated multpler, the bt error s hgher wth one place, and more mportantly over 33.3% dfference n the worse decmal error s generated. On the other hand the average error seems to be over 16.41% better for the truncated mplementaton. Ths result has to be further verfed but even f t s correct the dfference n the maxmum absolute error s qute severe. The benefts are slghtly under 5.6% of the area reducton. For the Dadda multplers,the usage of truncated multpler produces much better results. The maxmum absolute bt error s the same,and there s only 3% dfference n the maxmum absolute decmal error. Also the average decmal error s ncreased wth 0%. The benefts are n the range of 5.6% area reducton. It s also mportant to note that the expected savngs n terms of area are slghtly below the actual grd square numbers after the synthess. For example accordng to [3] the Rato of the Area of Standard Vs. Truncated Array multpler should be Consderng the fact that the Multpler consumes 76.15% of the N-R Module area, we can expect that the savngs should be n the range of 17%. The actual savngs are under 6%! The reason for that s that the area savngs are somehow restrcted wth array multpler shape whch when truncated loses ts unque quadratc shape, therefore the place and route algorthms mght not be able to get the full advantage of the sub unt savngs. V. Concluson It can clearly be seen that there s a hgher ncrease n the naccuracy of the unt than the savngs of the area. The hgher error stll mght not be a serous ssue for many DSP processors especally n graphcs. It s mportant to note that even though the percentage ncrease seems to be hgh, the range of the error s stll well under 8% for maxmum error and 4% for average error. It s also curtal to note that ths study need to be further verfed. The resultng hgher Relatve Error for standard array multplers does not seem to make much sense. Also the expectatons that the Dadda multplers would produce hgher area were not met. Other than that ths study stll deals only wth 8-bt number, DSP Processors wth 8-bt words are very rare today and most mplementatons use 16-bt or 3-bt words. The study can easly be extended to 16-bt where the expectatons are for a further 8-10% area reductons wth mnmal cost n terms of accuracy. Most of the work for the 16-bt verfcaton s already completed (ncludng the C code and the Verlog fles), but snce the number of the vectors to be tested wll ncrease dramatcally t wll requre qute a bt more computatonal tme.

15 Fnally for further work, analyses of the power and delay ratos wll be benefcal. It s mportant to note that even though the power consumpton s expected to be proportonal to the area savngs [3]; t mght be even hgher when appled to the N-R Module. The reason for that s that the area savng are restrcted wth the fact that the shape of the multplers s not mprovng.

16 References [1] Erc Rce and Rchard Hughey Multprecson dvson on an 8-bt processor Proceedngs of the 13th IEEE Symposum on Computer Arthmetc, [] J. E. Stne Lecture Notes,Illnos Insttute of Technology,001 [3] M. J. Schulte, J. G. Jansen, and J. E. Stne. Reduced Power Dsspaton Through Truncated Multplcaton," n IEEE Alessandro Volta Memoral Internatonal Work-shop on Low Power Desgn, [6] M. J. Schulte and E. E. Swartzlander, Jr., Truncated Multplcaton wth Correcton Constant," n VLSI Sgnal Processng, VI,, [5] E. J. Kng and E. E. Swartzlander, Jr., Data-Dependent Truncated Scheme for Parallel Multplcaton," n Proceedngs of the Thrty Frst Aslomar Conference on Sgnals, Crcuts and Systems, [7] Kent Eugene Wres, Arthmetc Unts for Dgtal Sgnal Processng and Multmeda, Lehgh Unversty,000 [8] Y. C. Lm, Sngle-Precson Multpler wth Reduced Crcut Complexty for Sgnal Processng Appl-catons," IEEE Transactons on Computers, vol. 41, no. 10, pp. 1333{1336, 199. [9] M. J. Schulte and E. E. Swartzlander, Jr., Truncated Multplcaton wth Correcton Constant," n VLSI Sgnal Processng, VI, pp , [10] S. S. Kdamb, F. El-Gubaly, and A. Antonou, Area Effcent Multplers for Dgtal Sgnal Processng Applcatons," IEEE Transactons on Crcuts and Systems II: Analog and Dgtal Sgnal Processng,vol. 43, no., pp , [11] E. J. Kng and E. E. Swartzlander, Jr., Data-dependent Truncated Scheme for Parallel Multplcaton," n Proceedngs of the Thrty Frst Aslomar Conference on Sgnals, Crcuts and Systems, pp ,1998. [1] K. Bckersta_, M. J. Schulte, and E. E. Swartzlander, Jr., Parallel Reduced Area Multplers," Journal of VLSI Sgnal Processng, vol. 9, pp , 1995.