register:a group of binary cells suitable for holding binary information flip-flops + gates
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1 9 차시 1
2 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flip-flops + gates control when and how new information is transferred into the register counter:a special type of register that goes through a predetermined sequence of states 2
3 outputs can be sampled at anytime from the register R input? 3
4 Register with parallel load loading : transfer of new information into a register needs synchronization of all flip-flops D input rather than C input for control the parallel operation 4
5 when load input=1, I inputs are transferred into the register when load input=0, no change why need the feedback connection? No no-change with D flip-flop. 5
6 6.2 Shift Registers shift register : a register capable of shifting its information in one or both directions How to control the shifting operation? 6
7 Serial transfer 7
8 why circulate in shift register A? to prevent loss of information stored in the source register shift control input : determines when and by how many times the registers are shifted (4-bit register case) 8
9 difference between serial and parallel modes of operation? 9
10 4-bit parallel adder 10
11 serial addition How does it work? Role of D flip-flop? 11
12 addition 1. Initially, A and D are cleared. 2. First number is added from B, and stored in A 3. Second number in B is added to A, and the sum is stored in A. 12
13 Comparison with parallel adder (Fig. 4.9) parallel-load capability vs. shift register n full-adder circuit vs. 1 full-adder + 1 carry flip-flop pure combinational circuit vs. sequential circuit 13
14 Let s design the serial operation - assume two shift registers for two numbers - let the serial output from the registers be x and y - exclude the registers from the sequential circuit, and include them later - use a JK flip-flop for storing the carry 1. State table? input : x, y present state : Q 14
15 2. flip-flop input equation? 15
16 J K Q Q xy x' y' ( x S x y Q y)' 16
17 Universal shift register capabilities of general shift registers clear control clock input to synchronize shift-right control serial input and output lines shift-left control serial input and output lines parallel load control n input lines n parallel output lines control state that leaves the information in the register unchanged even with clock pulses shift-right and left : bidirectional shift register shift and parallel load capability : universal shift register 17
18 18
19 19
20 HDL for FPGA
21 HDL HDL Hardware Description Language FPGA - Field programmable gate array Altera Cyclone IV, Cyclone V. Xlinx Zynq, Spartan
22 FPGA & HDL CPU is the aggregate composed of a number of Logic circuits. Since the structure is fixed, the performance is good, but It s Structure can not be modified. CPU has a number of features, the user use some of the functions of the CPU through the programming
23 FPGA & HDL FPGA is used in two main purpose. When the user wants to have the high performance for a particular function. For simulation.
24 FPGA & HDL FPGA application areas. - Stereo Camera (3D FPV)
25 FPGA & HDL FPGA application areas. Network facilities
26 FPGA & HDL The Verilog language describes a digital system as a set of modules. Each module has an interface to other modules as well as a description of its contents. A module represents a logical unit that can be described either by specifying its internal logical structure for instance, describing the actual logic gates it is comprised of, or by describing its behavior in a program-like manner in this case, focusing on what the module does rather than on its logical implementation. The modules are then interconnected with nets, allowing them to communicate.
27 A Structural Description A simple NAND latch module ffnand(q, qbar, preset, clear); <= Module name output q, qbar; <= output declarations input preset, clear; <= input declarations g1 u1 (.out1(q),.out2(qbar),.in1(preset)) ; g2 u1 (.out3(qbar),.out4(q),.in2(clear)); endmodule
28 A Structural Description Nets Gates are connected by nets. Nets are one of the two fundamental data types of the language. Registers are the other data type. Nets are used to model an electrical connection between structural entities such as gates. A wire is one type of net. Other net types include wired-and, wired-or and trireg connections. The trireg net models a wire as a capacitor that stores electrical charge. Except for the trireg net, nets do not store values but only transmit values that are driven on them.
29 A Structural Description Hierarchical descriptions Several gates or modules are built into larger modules in a hierarchical manner. In a simple NAND latch example, NAND gates were used to build the ffnand module. This ffnand module could then be used as a piece of a larger module by instantiating it into another module. The use of hierarchical descriptions allows us to control the complexity of a design by breaking the design into smaller and more meaningful submodules. When instantiating the submodules, all we need know about them is their interface.
30 Simulating a Module A simple NAND latch to be simulated includes A structural description of a simple NAND latch The statements that will provide stimulus to the NAND gate instances The statements that will monitor the changes in the outputs. The monitor statement A simulation command to monitor and print a set of values when any one of the values changes %b represents a printing control for binary. The,, put extra spaces between the display of the time and the quoted string.
31 Simulating a Module Simulator Executes the statements in the initial statement and propagates changed values from the outputs of gates and registers to other gate module inputs. Keeps track of time, causing the changed values appear at some specified time in the future rather than immediately. The future changes are typically stored in a time-ordered event queue. When the simulator has no further statement execution or value propagation to perform at the current time, it finds the next timeordered event from the event queue, updates time to that of the event, and executes the event. Continues until there are no more events to be simulated or the user halts the simulation.
32 Simulating a Module How does the simulator work in this example? The first assignment statement #10 preset = 0; clear = 1; specifies the registers preset and clear will be loaded zero and one respectively 10 time units from the current time (time 0). At time 10, preset and clear are set to zero and one respectively, and then the changed values are propagated. At time 11, q becomes one, which is the result of preset being zero. The value of q is propagated to the input of NAND gate g2 which is then scheduled to propagate its changed output 1 time unit in the future. At time 12, qbar becomes zero.
33 Simulating a Module How does the simulator work in this example? The second assignment statement #10 preset = 1; specifies the register preset will be loaded one 10 time units from the current time (time 10). At time 20, preset is set to one, and q and qbar remain constant. The third assignment statement #10 clear = 0; specifies the register clear will be loaded zero 10 time units from the current time (time 20). At time 30, clear is set to zero and the latch changes state after 2 gate delays.
34 Simulating a Module How does the simulator work in this example? The fourth assignment statement #10 clear = 1; specifies the register clear will be loaded one 10 time units from the current time (time 30). At time 40, clear is set to one, and q and qbar remain constant. The last initial statement #10 $finish; stops the simulation and returns control to the host operating system at time 50.
35 Simulating a Module Results of simulating the simple NAND latch Time State 0 preset = x clear = x q = x qbar = x 10 preset = 0 clear = 1 q = x qbar = x 11 preset = 0 clear = 1 q = 1 qbar = x 12 preset = 0 clear = 1 q = 1 qbar = 0 20 preset = 1 clear = 1 q = 1 qbar = 0 30 preset = 1 clear = 0 q = 1 qbar = 0 31 preset = 1 clear = 0 q = 1 qbar = 1 32 preset = 1 clear = 0 q = 0 qbar = 1 40 preset = 1 clear = 1 q = 0 qbar = 1
36 Simulating a Module Results of simulating the simple NAND latch
37 Simulating a Module The four values that a bit may have in the simulator 1 : true (one) state 0 : false (zero) state x : unknown state z : high-impedance state Why were preset and clear defined as registers? A means of setting and holding the input values during simulation Wires do not hold values but merely transmit values.
38 Module Hierarchy Ports Must be declared to be inputs, outputs, or inouts. Vectors and scalars The square brackets construct declares the range of bit numbers, the first number being the most significant bit and the second being the least significant bit. The bit numbers used in the specifications must be positive. Registers, nets and ports declared to have a range of bits are said to be vectors. Single-bit registers, nets and ports are said to be scalars.
39 Module Hierarchy Association of ports The order of the names in the instantiation port list must match the order of ports in the definition. Analogous to the software situation where we need to know the order of parameters when calling a subroutine.
40 Module Hierarchy Operators ~ : Bitwise negation Complements each bit in the operand. ^ : Bitwise XOR Produces the bitwise exclusive OR of two operands. & : Unary reduction AND Produces the single bit AND of all of the bits of the operand. & : Bitwise AND Produces the bitwise AND of two operands. Unary reduction and binary bitwise ANDs are distinguished by syntax.
41 Module Hierarchy The assign statement Another way of describing a combinational logic function Called continuous assignment statement because the result of the logical expression on the right-hand side of the equal sign is evaluated anytime one of its inputs changes and the result drives the output in a simulation. Allows us to describe a combinational logic function without regard to its actual structural implementation, i.e., there are no instantiated modules. Part-select of a vector A selected range of bits from the entire vector is used in the operation.
42 Module Hierarchy The always statement Basis for modeling sequential behavior Essentially a while (true) statement Includes one or more procedural statements that are repeatedly executed. The procedural statements within the always statement execute much like a software program.
43 Module Hierarchy clock) q = data; When there is a negative edge on the clock input, then the value of the data input will be copied into register q. Behavioral descriptions Capture all of the functionality of the module. Leave the actual logical implementation open to the designer.
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