McGill University Faculty of Engineering FINAL EXAMINATION Fall 2007 (DEC 2007)

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1 McGill University Faculty of Engineering FINAL EXAMINATION Fall 2007 (DEC 2007) VERSION 1 Examiner: Professor T.Arbel Signature: INTRODUCTION TO COMPUTER ENGINEERING ECSE-221A 6 December 2007, Co-Examiner: Professor F.P. Ferrie Signature: STUDENT NAME AND SIGNATURE INSTRUCTIONS: MCGILL I.D. NUMBER This is a CLOSED BOOK examination. This is, in part, a MULTIPLE CHOICE examination. As such, the following warning applies: Warning: The Examination Security Monitor Program detects pairs of students with unusually similar answer patterns on multiple-choice exams. Data generated by this program can be used as admissible evidence, either to initiate or corroborate an investigation or a charge of cheating under Section 16 of the Code of Student Conduct and Disciplinary Procedures. MARK YOUR ANSWERS TO THE MULTIPLE CHOICE QUESTIONS ON THE ENCLOSED COMPUTER SHEET USING PENCIL ONLY. Each question is worth 1 mark, a wrong answer will receive 0. Space is provided on the exam in which to answer the short answer questions (21 to 24). DO NOT USE ANY OTHER EXAM BOOKS FOR ANSWERS TO BE MARKED. You are permitted REGULAR AND TRANSLATION dictionaries. FACULTY STANDARD CALCULATOR permitted ONLY. This examination consists of two parts; part 1 consists of 20 multiple choice questions, part 2 consists of a set of 4 short answer questions. The examination consists of a total of pages including this cover page. Please ensure that you have a complete examination paper BEFORE starting. Please sign this paper at the top of this page, write your name legibly, and read the instructions above. Initial each page of the exam paper in case the sheets should get separated. THIS EXAMINATION PAPER MUST BE RETURNED. Exam 2007A- 1

2 TEST QUESTIONS PART 1 - This part consists of 20 multiple choice questions. Indicate the correct answer to each question on the computer readable sheets provided. 1. Determine the best minimal canonical forms corresponding to the following sum of products form: (0,1,2,3,5,7,9,11,13,15) (a) ABD D (b) AB AD (c) AB AD (d) ( A B)( D) (e) AB D Answer is (e) A, B, C, D 2. Convert 6AA.E42 16 into its decimal equivalent. Remember to use the correct number of significant figures. (a) 1707 (b) (c) (d) (e) 1706 Answer: How many digits do we need after the decimal point? #digits10 = #digits16 * [log (16)/log (10)] = 3 * = So, rounding up, we need 4 digits after the decimal point = (6 * 16 2 ) + (A * 16 1 ) + (A * 16 0 ) + (E * 16-1 ) + (4 * 16-2 ) + (2 * 16-3 ) = (6*256)+(A*16)+(A*1)+(E*0.0625)+(4* )+(2* ) = = = Answer is (c) Exam 2007A- 2

3 3. An IEEE-like floating point representation is to be designed for a computer with a 48-bit register size. Assuming a 10-bit exponent, determine the bias for this representation. (a) 1023 (b) 1024 (c) 512 (d) 511 (e) 255 Answer: (d) 4. Which latch is implemented by the following circuit? +5V A X +5V B Y (a) SR latch (b) Edge-triggered flip-flop (c) Clocked SR latch (d) JK flip-flop (e) T flip-flop Exam 2007A- 3

4 Answer: Answer is (a) 5. Determine the setup time and the hold time of the following circuit: D Qms Clk (a) Tsu =3 Tg, Th =0 Tg (b) Tsu =3 Tg, Th =1 Tg (c) Tsu =4 Tg, Th =1 Tg (d) Tsu =4 Tg, Th =3 Tg (e) Tsu =5 Tg, Th =0 Tg Answer is (a) 6. A clocked JK flip-flop in toggle mode can lead to a RACE condition when: (a) (b) (c) (d) (e) J and K are both low at the same time. The output signal has a chance to work its way back to the input before the clock is pulled low. The setup time is too low. The clock is high for the duration of 1 gate delay. A race condition cannot occur with a JK flip-flop. Exam 2007A- 4

5 Answer is (b) 7. Consider the timing diagram below comparing the results of 2 different JK flip flops. Based on the outputs for the edge triggered (Qet) and master-slave (Qms) varieties, what can we conclude about the two different types of flip flops? (a) Edge-triggered flip flops are not susceptible to 1 s and 0 s catching. (b) Edge-triggered flip flops do not respond to J=K=1. (c) This edge-triggered flip flop is rising-edge triggered. (d) With master-slave flip flops, the output follows the input the entire time the clock is high. (e) Master-slave flip flops are basically counters. Answer: (a) 8. What is the output produced by the following snippet of C code? int a[] = {4, 3, 2, 1, 0}; int b = 3; b = (b & 5) << 2; printf("%d ",a[b--]); (a) 4 (b) 3 (c) 2 (d) 1 (e) 0 Answer: (e) 9. Which of the following statements is false regarding ROMs: (a) A ROM is useful when the same computations are performed often. Exam 2007A- 5

6 (b) A ROM is basically a look-up table. (c) For a 3-input ROM, there are 2 3 output lines. (d) The input to a ROM is an address, and the outputs are the data lines. (e) As the numbers of inputs grows on a ROM, the number of entries grows exponentially. Answer: (c) 10. A design engineer is attempting to fabricate a 32-bit full adder using a single level of carry generation. What is the expression for term c 3 assuming that carry propagation: p i = a i + b i, and generation, g i = a i b i, are available inputs? (a) c 3 = g 3 + p 3 g 2 (b) c 3 = g 3 + p 3 g 2 + p 2 g 1 (c) c 3 = g 2 + p 2 g 1 + p 2 p 1 g 0 (d) c 3 = g 2 + p 2 g 1 + p 2 p 1 g 0 + c 0 p 2 p 1 p 0 (e) c 3 = g 2 + p 2 g 1 + p 2 p 1 g 0 + c 0 p 2 p 1 g 0 Answer: (d) Exam 2007A- 6

7 11. Which of the following statements is false regarding the Universal Counter Cell below: (a) When M0=M1, the JK flip flop becomes a D flip flop. (b) When M1=1, M0=0, the cell counts up. (c) When M1=0, M0=1, the JK flip flop becomes a T flip flop. (d) The cell can count up, count down, load new numbers and hold the current value. (e) When M1=1, M0=0, the cell becomes a down counter. Answer: (b) Exam 2007A- 7

8 12. Consider the following C code: a = (a!= b); Which of the following Assembly code instructions is the correct translation of this function? Assume a is stored in register $10 and b is stored in register $20. Answer: (b) (a) beq $10, $20, equal ori $10, $0, 0 bne $0, $0, done equal: ori $10, $0, 1 done: (b) bne $10, $20, noteq ori $10, $0, 0 beq $0, $0, done noteq: ori $10, $0, 1 done: (c) beq $10, $20, equal ori $20, $0, 1 bne $0, $0, done equal: ori $20, $0, 0 done: (d) bne $10, $20, noteq ori $10, $0, 1 beq $0, $0, done noteq: ori $10, $0, 0 done: (e) bne $10, $20, noteq ori $10, $0, 1 beq $0, $0, done noteq: ori $20, $0, 0 done: Exam 2007A- 8

9 13. Given the following assembly language instruction: sll $12, $13, 3 and the MIPS documentation at the end of this exam, what is the translation of the instruction into MIPS machine code? (a) 0x0000dc30 (b) 0x0000cd30 (c) 0x000d60c0 (d) 0x000c68c0 (e) 0x000c0d30 Answer: (c) 14. Which of the following functional units is NOT required for a branch operation? (a) The register file. (b) An ALU for adding. (c) Data memory. (d) Hardware to sign-extend a 16-bit number to 32 bits. (e) A multiplexer. Answer: (c) 15. Which of the following statements is true regarding Booth s algorithm? (a) Booth s algorithm always leads to improvements in unsigned multiplication. (b) Booth s algorithm is a method for speeding up signed division. (c) Booth s algorithm results in fewer additions and subtractions than traditional multiplication strategies only if the 1 s in the multiplier are grouped into long blocks. (d) Booth s algorithm reduces the hardware requirements required for multiplication. (e) Booth s algorithm is a method for grouping the multiplier and remainder into 1 register during multiplication. Answer: (c) Exam 2007A- 9

10 16. Which instruction consumes the longest possible path in a single-clock cycle processor? (a) Store. (b) Branch. (c) Jump. (d) Load. (e) And. Answer: (d) 17. A memory instruction requires a sign extension unit in order to: (a) Add 4 to the program counter. (b) Multiply the 16-bit offset by 2 while preserving the sign. (c) Convert the 16-bit offset into 32-bits while preserving the sign. (d) Convert the 16-bit offset from words to bytes. (e) Convert the 16-bit offset to its twos complement representation. Answer: (c) 18. Which of the following is false regarding a multi-cycle processor implementation? (a) Compare to the single-cycle implementation, the amount of hardware is increased. (b) In a multi-cycle implementation, each step in the execution will take 1 cycle. (c) The multi-cycle implementation allows a functional unit to be used more than once per instruction. (d) In a multi-cycle implementation, instructions are permitted to take different numbers of clock cycles. (e) A single memory unit is used for both instructions and data. Answer: (a) Exam 2007A- 10

11 19. In the design discussed in class, the ALU controller controls which operation the ALU should perform. Determine the correct ALUop control bits (feeding the ALU controller) for the operations of: lw, beq, and. (In order: lw, beq, and) (a) 00, 01, 10 (b) 00, 00, 00 (c) 10, 10, 10 (d) 00, 00, 10 (e) 10, 01, 10 ALUop Meaning 00 Add 01 Sub 10 Get function from function bits (Assume single-cycle implementation) Answer: (a) Exam 2007A- 11

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13 20. The diagram below illustrates a single-cycle processor architecture with a particular instruction s datapath highlighted (excluding the instruction fetch). Which of the following instructions is highlighted? (a) Branch equal (b) Add (c) Load (d) Jump (e) Store Answer: (c) PART 2 of this exam starts on the next page. Please turn over the page and begin Part 2 NOW! Exam 2007A- 13

14 PART 2 - This part consists of 4 short answer questions. Each question is worth 10 marks. Write your answers to the question in the space provided on this exam paper. Do not use extra paper - any answers written outside of the allowed space will not be marked. 21. (a) Convert the following IEEE 754 single precision number to its decimal (base 10) equivalent. Be sure to use the correct number of significant figures and show all your work. (4 marks) 87A Solution: Start by converting to binary: Regroup as sign, exponent, and mantissa: So, the sign bit = 1: it's a negative number (0.25 marks) The exponent is = 15 This is offset by 127, so the actual exponent is: -112 (0.5 marks) Add a 1 to the start of the mantissa to get the whole mantissa: = = (1 mark) So far, we have the answer as: * But need to have it as a power of 10, so just multiply it out: (1 mark each part) How many decimal digits do we need? Since there were 24 binary digits, compute: #decimal digits = 24 * log (2) / log (10) #decimal digits = 7.2, or 8 digits.(0.25 marks) So, rounding, and taking into account the sign, we get the solution: Exam 2007A- 14

15 * Exam 2007A- 15

16 (b) Consider the following truth table corresponding to the function F(A,B,C,D). d refers to don t cares : A B C D F d d d d d i. Determine the minimal product of sum forms for this function. (2 marks) Solution: Product of sums = (A+C )(A +C) ii. Show how this function can be implemented using a multiplexer. (2 marks) Solution: Exam 2007A- 16

17 16 bit mux with inputs: (Note that other options were possible) F 1 1 d 0 d 1 0 d d d bit mux with inputs: (Note that other options were possible) F D 1 1 D 0 0 D 0 D D D D bit mux with inputs C, C (A is the selector): Exam 2007A- 17

18 iii. Show how this function can be implemented using NOR-NOR logic. (2 marks) A' C C' A F Exam 2007A- 18

19 +5V +5V ECSE-221A 22. (a) For the circuit shown below, answer the following questions. You may assume that the circuit has been initially cleared to (Q1=0, Q0=0). +5V M J C S Q K R Q Q1 J C S Q K R Q Q0 0 1 i. Determine the next state equations for each flip-flop (Q1 and Q0). (4 marks). Solution: Qˆ = JQ + K Q (-1 if JK wrong) Qˆ 1= JQ1 + K Q1 = JQ1 because K =1 J = XNOR (M, Q0) = MQ0+M Q0 Qˆ 1 = JQ1 = ( MQ0+M Q0 ) Q1 = MQ1 Q0 + M Q1 Q0 Qˆ 0= JQ0 + K Q0 = JQ0 because K =1 J= NAND (Q0, Q1) = (Q0 Q1) = Q0 +Q1 = Q0 + Q1 Qˆ 0= J Q0 = (Q0 + Q1 )Q0 = Q1 Q0 ii. Determine the corresponding state transition table. (2 marks) M Q0 Q1 Qˆ 0 Qˆ Exam 2007A- 19

20 i. Assume that the XNOR gate has Tpd=1.5 ns and the NAND gate has Tpd= 1nS. The timing parameters for flip-flops Q0 are Tpd=0.5nS, Th=0.2nS, and Tsu=0.4nS. Flip-flop Q1 has Tpd=0.7nS, Th=0nS, and Tsu=0.2nS. Determine the maximum frequency of operation for this circuit. (2 marks) Solution: Highest Tpd, Th and Tsu are respectively 0.7ns, 0.2ns and 0.4ns. Longest combinational logic path is the XNOR gate, 0.5 ns longer than the NAND gate. The Tcl is therefore 1.5ns. Putting these together gives minimum time Tmin = Tcl + Tsu + Tpd = 1.5ns + 0.4ns+ 0.7ns = 2.6ns Fmax = 1/Tmin = 2.6ns = MHz iv. The combinational logic in the above circuit is to be replaced by read only memory (ROM). Determine the number of address and data lines required and the ROM contents. (2 marks) Solution: 3 address lines 2 data output lines (1 mark) Address: Data: (1 mark) Answer depends on input order) Exam 2007A- 20

21 23. (a) Below is one possible design for a 32-bit ALU with the capacity for the operations: AND, OR, ADD, SUB and LESS: The contents of the 1-bit ALU for the Most Significant Bit are found below: Exam 2007A- 21

22 i. What values do the control lines: Binvert and Operation take on in order to perform the operation for set-less-than? (1 mark) Solution: Binvert: 1 Operation: 11 ii. Suppose we wish to add the capacity to perform NOR operations. We would like to modify the cell slightly without making too many large changes to the existing design, i.e. we are not permitted to add an additional separate NOR gate. Supposing that the input a has its own inverter and multiplexer, similar to the design for b. Let the control line for a s multiplexer be Ainvert. What values should we assign for Ainvert, Binvert and Operation to permit us to perform the NOR operation? (2 marks) Solution: Ainvert: 1 (0.5 marks) Binvert: 1 (0.5 marks) Operation: 00 (And) (1 mark) Exam 2007A- 22

23 (b) Consider the following implementation for the division of 2 32-bit numbers: i. What improvements can you make to this hardware design in order to simplify it and make it more efficient (in terms of the hardware)? Explain your modifications and re-draw the divider with the modified hardware. (2 marks) Exam 2007A- 23

24 ii. Show the steps of the more efficient restoring division algorithm described in class with the modified design from i. Use the following steps: (2 marks) 0. INIT: Place divisor in the Divisor register. Place dividend in the Remainder register (0.25 marks). 1. SHIFT: Shift the Remainder register to the left 1 bit. (0.5 marks) 2. SUBTRACT: Subtract Divisor register from the upper half of Remainder register and leave result there. (0.5 marks). 3. TEST RESULT: (a) If the result is 0 or positive: Shift Remainder register to the left setting the rightmost bit to 1. (0.25 marks) (b) If the result is negative strictly: Restore the initial value by adding the Divisor register to the upper part of the Remainder register leaving the sum there. Shift the remainder register left setting rightmost bit to 0. (0.25 marks) 4. COUNT TO SEE IF DONE: If 32 nd repetition, then done, else goto subtract step. DONE: Shift upper part of Remainder register right 1 bit. (0.25 marks for this step and above.) iii. Supposing we modify the final design slightly to consider the division of 2 4-bit numbers. Show content of the remainder register at each iteration for the following numbers: Show all work. (3 marks) 0101 / 0010 Solution: (b) (b) (a) Exam 2007A- 24

25 (b) Done marks for each step + init & final answer. Exam 2007A- 25

26 24. (a) Implement the following C code in MIPS: (4 marks) swap (int a[], int j) { int tmp; } tmp = a[j]; a[j] = a[j+1]; a[k+1] = tmp; Use this register assignment: $3: j $4: pointer to a[0] $15: scratch $16: scratch $17: register for array accesses, i.e. $17 points to a[j] Remember to save and restore the context using the stack. Solution (from notes): # # save context of caller (1 mark for saving and restoring properly)) # swap: addi $29, $29, -12 sw $15, 0($29) sw $16, 4($29) sw $17, 8($29) # # main procedure body # sll $15, $3, 2 add $17, $4, $15 # Turn j into array offset # Add offset to base, $17 points to # a[j] (1 mark to here) lw $15, 0($17) # tmp1 $15 = a[j] lw $16, 4($17) # tmp2 $16 = a[j+1] Exam 2007A- 26

27 (1 mark to here) sw $16, 0($17) # a[j] = a[j+1] sw $15, 4($17) # a[j+1] = a[j] (1 mark to here) # # restore context of caller # lw $15, 0($29) lw $16, 4($29) lw $17, 8($29) addi $29, $29, 12 Exam 2007A- 27

28 (b) Consider the following single-cycle implementation for the MIPS architecture below: i. The controller (not seen here) generates a signal called branch to indicate that a branch instruction is currently being implemented. Modify the design above, showing how the control signal for the multiplexer PCSrc is generated given the branch control line and the rest of the circuit. (1 mark) ii. Fill in the values that the following control lines take on during the 2 operations below: (2 marks) lw $4, 50($5) beq $4, $8, loop Recall that the values can be 1, 0 or X (don t care). Operation RegDst ALUSrc RegWrite MemtoReg lw beq X 0 0 X Exam 2007A- 28

29 iii. Assume that the datapath has the following parameters: For all registers: Tsu = 2ns, Th = 0ns, Tpd=10ns For all multiplexers: Tpd = 1ns For the register file: Ta = 3ns (Access time for reading) For all ALUs: Tpd = 20ns For all memory: Ta = 35ns (for both reading and writing operations) All other delays may be neglected. Given the timing parameters, estimate the maximum clock frequency for this datapath. (3 marks) Longest path is for a lw operation. (0.25 marks) Tcl = (Mem(inst)+ Reg + Mux + ALU + Mem(Data) + Mux) = = 95 ns (1.5 marks) Can assume that the first Mux delay time is in parallel with the rest (0.25 marks) Fmax = 1/(95 +12) = MHz (0.5 marks for formula. 0.5 marks for correct answer.) Exam 2007A- 29

30 Exam 2007A- 30

31 Exam 2007A- 31

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