CSCI 402: Computer Architectures

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1 CSCI 402: Computer Architectures Instructions: Language of the Computer (2) Fengguang Song Department of Computer & Information Science IUPUI Memory Operands Two tribes: Big Endian: Most-significant byte stored in low address of memory Little Endian: Least-significant byte stored in low address of memory E.g., Intel machines 0x

2 Byte Swap Problem GH 3 EF 2 CD 1 AB 0 Big Endian increasing byte address AB 3 CD 2 EF 1 GH 0 Little Endian Memory layout of a number of ABCDEFGH Each system is self-consistent, but causes problems when they need communicate! How about one byte: 0xAB? Does endianness matter? 3 Memory Alignment Memory Alignment (2 nd issue) Although computers are byte-addressable, memory is organized in aligned words. Alignment An n-byte data type is at an address that is a multiple of n n may be 1, 2, 4, 8, 16 (power of 2) Compiler is responsible for maintaining aligned data objects Simplify hardware design and reduces memory access time Alignment: Require objects fall on address that is multiple of their size. Endianess is one issue. Aligned Cannot be put anywhere Word? must be aligned with addresses=4*k Not Aligned 4 2

3 Now, Combine Endianness and Alignment When do you need to consider Endianess, Alignment?, 5 1st Example of Memory Operand C code (1 array operand): g = h + A[8]; //Array of words g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires an offset of 32 lw $t0, 32($s3) add $s1, $s2, $t0 # load word offset base register 6 3

4 Memory Operand Example 2 C code (Now, 2 array operands): A[12] = h + A[8]; h in $s2, base address of A in $s3 Compiled MIPS code: lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word 7 Registers vs. Memory Registers are faster to access than memory And use less energy Operating on memory data requires loads and stores Require more instructions to be executed Compiler must utilize registers to store variables as much as possible Only spill to memory for less frequently used variables (called register spilling ) 8 4

5 Immediate (Constant) Operands This is the 3 rd type of operand. 50% of instructions take a constant as input Based on SPEC CPU2006 benchmark Then, how to specify immediate data in an instruction? addi $s3, $s3, 4 However, no subtract-immediate instruction We can use a negative constant that is, addi $s2, $s1, -1 Design Principle #3: Make the common case fast Instructions using small constants are very common Q: Why addi should be faster than add? Immediate operand avoids a load instruction 9 The Constant Zero MIPS Register 0 ($zero) stores the constant 0 It is a special register Cannot be overwritten Is useful for common operations e.g., move data between registers: $s1 -> $t1 add $t1, $s1, $zero Q: Since registers are so important, should vendors (Intel/AMD) increase #registers very quickly (e.g., similar to Moore s law)? Because registers are related to ISA. But ISA is changed very slowly. 10 5

6 Format of the lw/sw instruction lw $register Address Address is represented by: Offset($R) //what does it mean? Address = Offset (in bytes) + Value stored in $R Similarly, sw $register Address 11 So far: Instructions? operations? operands? Number representation in HW (integer) Instruction representation in HW Logical operations in MIPS 12 6

7 2.4 How to Represent Unsigned Integers? Given an n-bit binary number: x n-1 x n-2 x 1 x 0 x = x + n-1 n n xn-22 +! + x12 x02 n Number the bits from right à left n Least significant bit à most significant bit. n Range: [0, 2 n 1] n Example n n = = = MIPS uses 32 bits n 0 to (i.e., +4,294,967,295) n Has issue of integer overflow What is wrong? unsigned int i; for(i = 1000; i >= 0; --i) { do_sth(); } 13 Next, How to Represent Signed Integers? Given an n-bit binary number, Leading bit=1 à Negative x n-1 x n-2 x 1 x 0 x = -x + n Range? n-1 n n xn-22 +! + x12 x02 2 n 1 to +2 n 1 1 n Example (a 32-bit signed integer) n = = 2,147,483, ,147,483,644 = 4 10 n MIPS uses 32 bits n 2,147,483,648 to +2,147,483,

8 2s-Complement Signed Integers Bit 31 is called sign bit Imbalance issue: ( 2 n 1 ) can t be represented! Then what is it? Positive numbers have the same 2s-complement representation Some special numbers 0: : Most-negative: Most-positive: How to Negate a Number Quickly Trick: Complement the number and add 1 Complement means 1 0, 0 1 Example: how to negate +2 10? n 2 = n 2 = = n If we negate the above number again? Question: But why this method works? x + x = = 1 x +1= x 16 8

9 Sign Extension There is an issue to copy a shorter number to a longer register e.g., copy a 4-bit number to an 8-bit register You must preserve the original numeric value e.g., copy to an 8-bit register? e.g., copy ? I don t know In the MIPS instruction set lw: both are 32-bit, no problem lb: need to extend the loaded byte to 32 bits Sign extension: Replicate the sign bit to the left c.f. unsigned values: extend with 0s (e.g., lbu) Examples: 8-bit to 16-bit +2: => : => How to Represent Instructions? We write add $s0, $s1, $s2, ß but it is assembly code Instructions are encoded in a binary format MIPS instruction? Encoded as a 32-bit word (fixed size) Has ONLY 3 instruction formats to encode opcode, register numbers, Need to map register names to register numbers $t0 $t7 are reg s 8 15 $t8 $t9 are reg s $s0 $s7 are reg s

10 MIPS R-format Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits MIPS s instruction fields Always 32 bits op: operation code funct: function code (extends opcode) rs: 1st source register number rt: 2nd source register number rd: destination register number shamt: shift amount (0 for now) 19 An R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 $t0 $t7: reg s 8 15 $t8 $t9: $s0 $s7: reg s special $s1 $s2 $t0 0 add =

11 Bitwise Logical Operations The following Instructions are used for Bitwise Manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT ~ ~ nor n Useful for extracting and inserting groups of bits in a word 21 sll $rd $rt #bits Bitwise Shift Operations (R-type) op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Encoding: op=0, funct=0 or 2 shamt: how many positions to shift: 5 bitsà 32 possible amounts to shift rs: unused, rt: source operand; rd: dest Shift left logical (sll) Shift left and fill with 0 bits sll by i bits à multiplies by 2 i Shift right logical (srl) Shift right and fill with 0 bits srl by i bits à divides by 2 i (unsigned only) 22 11

12 Bitwise AND Operations AND is useful to mask bits in a word Reset some bits to 0 and $t0, $t1, $t2 $t2 $t1 $t Bitwise OR Operations OR is useful to include bits in a word Set some bits to 1, leave others unchanged or $t0, $t1, $t2 $t2 $t1 $t

13 Bitwise NOT Operations NOT is useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b means NOT ( a OR b ) nor $t0, $t1, $zero Register 0 $t1 $t Bitwise Logical Operations Problem 1: How to isolate a segment in a word? Method 1: use AND a static way Method 2: A shift left followed by a shift right more flexible Problem 2: Set the bits from 5 to 12 in a 32- Given an integer x, bit word? unsigned in mask = -1; mask = mask << 24; mask = mask >> 19; x = x mask; 26 13

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