Cmpt 150 The Freescale CPU12 March, The Freescale HC12

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1 The Freescale HC12 The instruction set architecture that we will use for assembly language programming is the HC12 ISA. Most recently, Freescale Semiconductor manufactured many System on Chip (SoC) implementations based on the HC12 core 1 Figure 1 shows a block diagram of a typical SoC built around the HC12 core. In terms of what we ve learned so far in the course, the single-cycle implementation of the Mano Simple Computer ISA occupies the boxes labelled CPU, RAM, and Flash EEPROM. The RAM and Flash EEPROM correspond to the Data Memory and Instruction Memory, respectively. 1 Motorola was the original designer of the HC12 instruction set architecture and implementations. Freescale Semiconductor started as a division of Motorola and was spun off as a separate company in HC12 Core CPU Central Processing Unit MMC Module Mapping Control RAM 2KB - 14KB BDM Background Debug Mode INT Interrupt BKP Breakpoint MEBI Multiplexed External Bus Interface STAR Bus EEPROM 1KB - 4KB Flash EEPROM 32KB - 512KB Port A (8-bit) Port B (8-bit) Port E (8-bit) Port K (8-bit) I.P. Bus Interface I.P. Bus Timer... D/A digital/analog conversion A/D analog/digital conversion SPI synchronous serial i/o SCI asynchronous serial i/o Figure 1: Block Diagram of a Typical SoC using the HC12 Core ([1, Figure 1-1]) 1

2 The box labelled EEPROM is used for configuration parameters. A SoC is typically used in applications where embedded computer systems control mechanical or electrical systems. To do this, the SoC needs to be able to communicate with the world. The I.P (Integrated Peripheral) Bus is used to communicate with interface circuitry that s fabricated on the chip along with the HC12 core and memory. Typical functional units include synchronous and asynchronous serial i/o, analog to digital (a/d) and digital to analog (d/a) converters, and timers. The four 8-bit ports, A, B, E, and K, can be used in various combinations for parallel communication with the world. Typically each pin is programmable as an input, output, or bi-directional input/output. The MEBI module is responsible for controlling these ports. The block labelled MMC, module mapping control, is responsible for mapping all the various blocks (memory and peripherals) to specific addresses in the 64K (16-bit) address space of the HC12. The core communicates with the peripherals in exactly the same way that it communicates with memory, by reading or writing to specific addresses. The block labelled INT handles interrupts. Interrupts are a way for external devices to get the attention of the processor even though it s currently doing something else. An interrupt causes execution of the current program to pause while the processor executes a special type of subroutine called an interrupt service handler. When the handler completes, the interrupted program resumes. The processor hardware ensures that this interruption is transparent to the interrupted program. The blocks labelled BDM and BKP are hardware assistance for debugging. 2

3 The Programmer s Model The programmer s model consists of those CPU registers and FFs which are visible to the programmer. Another way of putting this is that the programmer s model consists of the registers referenced by the assembly language instructions (the ISA). One can argue that the instruction register and the memory are also part of the programmer s model, but they re usually not shown explicitly. The programmer s model for the HC12 is shown to the right. There is a program counter, PC. There are two 8-bit registers, A and B, which can be used for general-purpose computation. They can also be used as a pair, forming a single 16-bit register D. The HC12 is capable of both 8-bit and 16-bit computations A B D 15 0 X 15 0 Y 15 0 SP 15 0 PC S X H I N Z V C overflow zero negative interrupt mask half carry NMI mask stop mask carry The rest of the registers are performing new functions, so we ll take a little more time with them. The HC12 provides hardware support for a type of data structure called a stack. A stack is characterised by the way in which data stored in the stack is accessed, a last-in, first-out (LIFO) ordering. This means that each successive item of data placed on the stack covers the previous item, so that the most recent additions must be removed to get to prior values. Placing an value on a stack is called a push operation, and removing a value is called a pop. Stacks are typically implemented in RAM memory. The location containing the most recently added data item is called the top of the stack. The stack pointer, SP, contains the memory address of this location. It is automatically altered by a number of HC12 instructions which add or remove data from the stack. 3

4 In the Simple Computer, the value of a register was used as the address for a memory read (load) or write (store) operation. The HC12 provides two index registers, X and Y (also called IX and IY), that provide dedicated support for addressing memory. Unfortunately, because they are dedicated to this use, they are not easy to use for general-purpose computation. The HC12 has a whole set of condition codes and control bits, grouped into a condition code register, CCR. The zero (Z), negative (N), overflow (V), and carry (C) condition codes serve the same function as their counterparts in the Simple Computer. They are set by many (but not all) instructions to reflect the value produced by the most recent ALU operation. The half-carry (H) condition code provides limited help for BCD arithmetic; it specifies the carry between bits 3 and 4 within a byte. The stop (S) mask bit and the two interrupt (I and X) mask bits enable or disable hardware functions. The HC12 instruction set includes a stop instruction which actually stops the on-chip oscillator that generates the clock signal. In many embedded control applications, executing a stop could cause physical damage; setting the S bit causes the stop instruction to behave as if it were a nop instruction. The I and X bits enable or disable interrupts. scope of this course, so we ll leave it at that. Interrupts are beyond the One point to notice about the condition codes. In the Simple Computer, the value of the condition codes (Z, N, C, V) was determined by the values currently being gated through the Function Unit. The value was calculated by combinational logic and changed when the operands changed. In the HC12, the condition codes are latched in FFs. Pay attention to the specifications of individual instructions. Some instructions will change the condition codes, some will not, and you can use this to your advantage. HC12 Assembly Language There are two broad organising principles for assembly languge: instruction types (or classes), and addressing modes. Let s start with instruction types. majority of instructions: At the top level, three classes cover the Data transfer instructions are concerned with the movement (but not the transformation) of data. 4

5 This group includes instructions which transfer data between CPU registers, and between CPU registers and memory. The first subgroup is often called register-register instructions, the second register-memory or load/store instructions. Arithmetic/Logic instructions are concerned with the transformation of data. These instructions transform source operands and (usually) place the result in a destination, so they do specify data movement, but it s the data transformation that s the distinguishing characteristic. The types of transformations typically included are integer arithmetic (addition, subtraction, and usually simple multiplication and division), logical (boolean AND, OR, NOT, XOR, and single bit test and set), and shift and rotate. At the hardware level, shifts and rotates may be implemented with hardware distinct from the hardware used for integer arithmetic and it s common to see them classified as their own separate instruction group. Flow-of-Control instructions, also commonly called program control instructions, are the means by which an assembly language programmer specifies changes to the default flow of instruction execution. They include jumps, conditional branches to choose the next instruction based on data values), and subroutine linkage instructions (which allow a single copy of a sequence of instructions to be used from many places in a program). What do we see in the HC12 instruction set? In the data transfer class, we have Load and Store: We can load any of A, B, D, SP, X, or Y from a memory location, or store their content to a memory location. Transfer and Exchange: We can transfer any of A, B, D, SP, X, Y, or CCR to any of A, B, D, SP, X, Y, or CCR, and we can exchange values between any of the registers. Where the transfer is from an 8-bit register to a 16-bit register, we can choose zero-extension or sign-extension of the 8-bit value. Move: We can move data from one location to another in memory. Stacking: As mentioned, a stack is a very useful structure for supporting the execution of programs. Call and return from subroutines is one use. As we ll see, the stack also supports local variables. Because it s such a useful structure for implementing the constructs of modern programming languages, the HC12 provides a set of instructions to support a stack. In 5

6 addition to stack use that s defined in support of subroutine call/return and interrupt handling, it s possible for us to make use of the stack for variables and parameters, as long as we re careful not to interfere with subroutine and interrupt support. In the arithmetic/logic class, the majority of the operations expect one operand in A, B, or D and will place the result in the same register. The other operand comes from memory. Addition and Subtraction: We can add and subtract using A, B, or D and a memory operand. It s also possible to add A or B to X or Y (this is useful in address calculations). Multiplication and Division: Instructions to perform signed and unsigned multiplication. Eight-bit operands produce a 16-bit result; 16-bit operands produce a 32-bit result. The operands must be in registers defined for the instruction, and the result goes to a set of defined registers. Increment and Decrement: Adding and subtracting one are common activities, so much so that they get their own set of assembly language instructions. We can increment or decrement any of A, B, SP, X, or Y and we can increment or decrement an arbitrary memory location. Boolean Logic: We can perform any of AND, OR, XOR, or NOT. One operand is in A or B, the other in memory. There s a pair of instructions that AND or OR an 8-bit value with the CCR, to efificiently set or clear bits in the CCR. Clear, Complement, and Negate: Another set of common activities. In addition to instructions to clear, complement, or (two s-complement) negate an 8-bit value, there are a few specialised instructions to clear bits in the CCR. Shift and Rotate: Any of A, B, D, or a memory location can be shifted (logical or arithmetic) or rotated. Compare and Test: This set of instructions is placed in the arithmetic/logic class because they are at heart subtraction operations that discard the result. As with subtraction, one operand is in a register, the other in memory. The distinction between compare and test in the HC12 instruction set is that in a test the second operand is defined to be zero. Bit Test and Manipulation: These instructions clear, set, or simply test bits in a memory location. Turning to the flow-of-control instructions, we have 6

7 Short and Long Branch: Short and long branch instructions change the flow of instruction execution based on the values of the condition codes. The distinction between the two is the size of the offset that can be specified in the instruction short branches have a one-byte offset, long branches two bytes. A specialised pair of instructions (Bit Condition Branch) tests bits in memory. Loop Primitives: This instruction group implements common loop header functionality as a single instruction. Given an index in any of A, B, D, SP, X, or Y, increment or decrement the register, then test to see if it s zero or non-zero. The loop ends when the test is satisfied. Jump and Subroutine Linkage: The jump instruction simply transfers flow of control to some absolute memory location (as opposed to a branch which is relative to the PC). The instructions to call and return from a subroutine automatically stack the return address as part of the instruction execution. There are some other groupings in the HC12 manual that are worth a mention: Index Register Manipulation and Pointer and Index Calculation: You ll notice that these are collections of instructions from other groups, brought together because they are useful for calculating addresses. That s the purpose of the index registers. Condition Code Test and Manipulation is another group collected from other groups to emphasise their utility for manipulating the condition codes. Interrupt: These instructions support the handling of interrupts. You can think of an interrupt as a subroutine call that can occur at any time during the execution of other code. Special effort must be taken to ensure that this diversion is completely transparent to the code that s interrupted. Diverting execution to service an interrupt is handled entirely by the hardware, but returning from the interrupt service routine requires a specialised instruction to undo the actions taken by the hardware. Other instructions allow the programmer to trigger the interrupt service sequence under program control. Stop, Wait, Noop, and Branch Never serve distinct but necessary purposes. Stop does exactly what it says it stops the on-chip clock, causing all activity to cease. The only way to resume activity is a hardware reset. Wait puts the system to sleep, waiting for an interrupt to occur to resume execution. No operation (nop) and branch never (brn) are useful for debugging a program without changing other parts of the machine code. They can be 7

8 used as replacements for any instruction, occupying space and giving the processor something to execute. The HC12 implements several types of specialised instructions for specific uses. BCD arithmetic instructions provide support for BCD addition. Several groups of instructions Fuzzy Logic, Maximum and Minimum, Multiply and Accumulate, and Table Interpolation are designed to support common operations required in industrial control algorithms. This is the raison d etre of SoC microcontrollers like the HC12. The Background Mode instruction enables hardware debugging support. Addressing Modes When it comes to finding the operands for an instruction, there are three possibilities: the operand can be encoded in the instruction; it can be stored in a register; or it can be stored in memory. The addressing mode for a given operand in an instruction specifies how to go about finding the operand. To make it easier to talk about addressing modes, we need to be precise about terminology. An operand of an instruction is a piece of data which is ultimately used in the instruction. A source operand is a piece of data which is an input to whatever action the instruction will perform. A result of an instruction is commonly referred to as a destination operand. The opcode of the instruction specifies the basic action performed by the instruction and the number of operands required. When the operand of an instruction must be fetched from memory, the addressing mode specifies how the memory address of the operand should be calculated. The memory address of the operand is called the effective address, and the calculation is the effective address calculation. An operand is said to be inherent, or implied, if the instruction opcode alone is sufificient to specify the addressing mode and no additional information is contained in the instruction. An operand is said to be explicit if additional information must be supplied in the machine language instruction in an operand field. 8

9 In the machine language of the MHC12, the opcode specifies both the number of operands and the addressing mode for each operand. One base assembly language instruction will have a number of distinct opcodes in machine language. For example, ADDA (A A + M[ea] for some effective address ea) has eight distinct machine language opcodes, each specifying a different addressing mode for the memory operand. The opcode of an instruction is usually one or two bytes. In the HC12 documentation, this is described as an opcode (one byte), possibly augmented by a pre- or post-byte qualifier. The actual choice of machine language opcode is made by the assembler, given the assembly language opcode and operand addressing mode(s) chosen by the programmer. An alternative used in some other machine languages is to specify the addressing mode as part of the operand field. The MHC12 belongs to a class of instruction set architectures called accumulator or single address machines. This means that in the majority of machine language instructions, at most one of the operands will be explicitly specified with an operand field, while the others will be specified inherently by the opcode. This is a very old ISA style and in the HC12 it has been extended to include a number of instructions which specify two or even three operands. Examples are the movw and movb instructions, the bclr and bset instructions, and the corresponding branch instructions brclr and brset. The accumulator style of ISA is not the only style, and you ll learn about others if you continue to study computer architecture. As you might expect, different ISAs require different ways of specifying the operands for an instruction. The basic instruction classes data transfer, arithmetic/logic, and flow-of-control do not change. HC12 Addressing Modes The HC12 provides a variety of addressing modes. The descriptions that follow will refer to the operand field. Some instructions will contain multiple operand fields, and each operand can use a distinct addressing mode. inherent immediate The location of the operand is specified by the opcode. The value of the operand is contained in the instruction. The operand field may be one or two bytes, to accommodate an 9

10 8- or 16-bit operand. The size of the operand is chosen to match the size of other operands (usually a register) used by the instruction. direct and extended register indexed The address of the operand is contained in the operand field of the instruction. The HC12 provides two variations of direct addressing. For the extended addressing mode, a 16-bit address is placed in the operand field of the instruction. This address is used as the effective address to fetch the operand from memory. The direct addressing mode, specifies only the least significant byte of the address in the operand field of the instruction. The most significant byte of the address is assumed to be 0x00. The effective address calculation concatenates 0x00 with the byte of address in the instruction to form an effective address in the range 0x0000 0x00ff. This is an optimisation to save program space and reduce execution time (by fetching one less byte of instruction) at the expense of limited address range. A CPU register specifier is contained in the operand field of the instruction. The operand is found in the register. The Simple Computer used register mode for the majority of its instructions; the operand field contained a 3-bit register specifier. One can argue that the HC12 doesn t have a register operand mode because all register operands are specified as inherent operands by the opcode. Generically, in an indexed addressing mode a CPU register (the base register) and an offset are specified in the operand field. The effective address calculation adds the contents of the register and the offset to produce the effective address of the operand in memory. The HC12 provides two 16-bit registers, X and Y (sometimes called IX and IY), whose primary use is to hold the memory address of operands. In addition, the SP and PC registers can be used as base registers. The instruction operand field can contain a five-, nine-, or 16-bit offset, or it can specify that the offset is held in one of the A, B, or D registers. The offset is assumed to be a two s-complement number. When the PC is used as the base register for indexed addressing in an instruction from the Flow-of-Control group, the addressing mode is called relative addressing. The justification for a 10

11 separate name is that the result of the effective address calculation is the address of the next instruction, rather than the address of an operand. autodecrement and autoincrement Autodecrement is a specialised form of indexed addressing. It has two forms, pre-decrement and post-decrement. In postdecrement, the effective address calculation uses the value in the base register as the effective address of the operand, then decrements the register by the amount specified in the offset. In pre-decrement, this is reversed: the base register is decremented and the resulting value is used as the effective address. The offset for this mode can range from one to eight. Autoincrement is exactly as autodecrement, except that the offset is added to the base register. There s one more twist: For any of the addressing modes that produce an effective address, we can add a level of indirection by declaring the effective address to be the address of the address of the operand. This is called indirect addressing. Typically the indirect addressing modes are named by adding indirect to the name of the base mode. The HC12 supports indexed-indirect addressing for indexed addressing using a 16-bit offset and indexed addressing using the value of register D as the offset. In the HC12, the registers X or Y are called index registers because the instruction set is structured to make it convenient to use them in indexed addressing. In general, the term index register can be applied to any register when it s used in an indexed addressing mode. The PC serves as an index register in the relative addressing mode but gets the name program counter because it s primary function is to point to the next instruction to be executed. The SP also serves as an index register, but gets the name stack pointer because of the instructions that are hardwired to use it (PSH, PUL, BSR, JSR, etc.) as a top-of-stack pointer. To give you a better feel for addressing modes, and illustrate some general assembly language programming techniques, let s look at a pair of examples. We ve seen from the Simple Computer that there s good reason for having the ability to calculate a memory address in a register. Otherwise, we have no access to the data manipulation capabilities of the Function Unit for address calculation. But what good is the ability to add a small offset to the address? Why is this so useful as to deserve implementation as an addressing mode? (Modes IDX and 11

12 IDX1 in the HC12 instruction set.) It turns out to be just the thing for working with structured data. Suppose, as an example, that we want to develop a suite of utility routines that will work with 3-D coordinate data, triplets of the form (x, y, z). Suppose that one byte per coordinate will be sufificient and we decide to store each triplet in three consecutive bytes. In Java we d write class ThreeDCoord { public byte x ; public byte y ; public byte z ; } As you know, creating an object of type ThreeDCoord involves asking for a block of space to store the values of x, y, and z. We might expect that they would be stored in consecutive locations in this block of space. How would we handle this in assembly language? Somewhere at the beginning of the assembly language source file, we ll put the following statements: ; Data structure offsets for 3-D coordinates. xcoord equ 0 ycoord equ 1 zcoord equ 2 Here, equ is an assembler directive (also called a pseudo-op). An assembler directive tells the assembler to do some action related to translating assembly code. The equ directive is used to define the name to the left as equal to the value to the right. Every time the assembler sees the name zcoord, it ll substitute the value 2. Now, here s a subroutine to add two 3-D coordinates. It expects that register X will contain the address of the first coordinate, register Y will contain the address of the second, and register D will contain the address where we re to put the sum. 12

13 ; Subroutine to add two 3D coordinates. ; X points to the first coordinate. ; Y points to the second coordinate. ; D points to the place to store the sum. ; Save the registers so we can use them freely. add3d: pshx pshy pshd ; Add the two x coordinates. Push the sum on the stack until ; we re ready to deal with it. The syntax xcoord,x specifies ; the indexed addressing mode using the X register. The ; effective address will be X+xcoord = X+0. xcoord,y will use ; the Y register as the base. ldaa xcoord,x adda xcoord,y psha ; Repeat for the y and z coordinates, pushing the y coordinate ; on the stack for temporary storage. ldaa ycoord,x adda ycoord,y psha ldaa zcoord,x adda zcoord,y ; Now pop the y and x coordinate sums into Y (y is in the most ; significant byte), and the destination address into X. Then ; store all three sums into the destination. We have to ; transfer the sums from Y to A,B to store them one at a time. puly pulx staa zcoord,x xgdy ; exchange A,B <-> Y staa ycoord,x stab xcoord,x ; Now restore the registers to their original values and ; return. xgdx puly pulx rts 13

14 The first comment to make about this program is that, just as in a high-level language, using meaningful names for constants is a good idea. Meaningful names greatly improve the readability of the program. The names xcoord, ycoord, and zcoord used for the offsets help to make the flow of the calculation clear. Using symbolic names insulates you from little annoyances like having your boss come by and tell you that the specifications have been revised and the data is now stored in reverse order as (z, y, x) triples. Instead of having to work your way through every line of code looking for numeric offsets, you simply go back to those first three lines and change them to ; Data structure offsets for 3-D coordinates. xcoord equ 2 ycoord equ 1 zcoord equ 0 Next, consider the sequence of psh operations at the start of the subroutine, and the matching set of pop operations at the end. It s very bad form to change the parameters of a subroutine unless this is specifically desired to return results. Here, X, Y, and D contain addresses, and it s quite likely that the calling code will want to use those addresses after add3d returns. On the other hand, the HC12 has precious few registers to work with, and we will have a very hard time writing the subroutine if we can t use X, Y, and D. The standard technique is to save the values of the registers on the stack at entry to the subroutine and restore them at the end. This is the purpose of the opening psh instructions and the closing pop instructions. A natural question to ask at this point is If three values are pushed at the start of the subroutine, why are only two values popped at the end? In this particular example, the value of D is the address of the destination triple. This was needed to store the result and was popped into X for that purpose. Hence restoring the value of D is achieved with xgdx instead of puld. Finally, let s look at the actual calculation. Stripped of comments, we have 14

15 ldaa adda psha ldaa adda psha ldaa adda puly pulx staa xgdy staa stab xcoord,x xcoord,y ycoord,x ycoord,y zcoord,x zcoord,y zcoord,x ycoord,x xcoord,x The first stanza adds the two x coordinates. But we can t leave the value in A; it s needed to add the y coordinates. So we push the result onto the stack for temporary storage. The second stanza does the same with the y coordinate, and the third with the z coordinate. We have no more calculation to do, so the value can remain in A. Now I have a problem: I ve used D for calculation, so it no longer holds the return address. And I ve pushed two more values (the x and y coordinate sums) onto the stack, burying the value of D. The solution is to pop the two sums into Y, which isn t holding a useful value at the moment. This exposes the destination address, which is popped into X where it will be easy to use as an address. Now I can store the value of the z coordinate sum. What about the x and y coordinate sums held in Y L and Y H, respectively? There is a sty instruction, but it will store Y H (y) in byte k and Y L (x) in byte k + 1, opposite to what s needed. One solution is to exchange the values of D and Y. Then I can store A and B individually, to the correct locations. Another solution would be to reverse the order of calculation for the x and y coordinate sums, so that the y sum would be pushed before the x sum. Then they would come off the stack into Y with the x sum in Y H and the y sum in Y L and a single instruction, sty xcoord,x would store both values. 15

16 We ve just seen that the ability to add a small (constant) offset to a (variable) base is just the thing to work with structured data like the 3-D coordinate structure. What about the opposite? Is it useful to have a constant base and a variable offset? Very definitely. This is the case for arrays. To work with an array of data, we again use indexed addressing, but this time a 16-bit offset is used to store the base of the array, and a register is used to calculate the offset into the array. (Mode IDX2 in the HC12 instruction set.) Indexed addressing adds the two to obtain the effective address of the array element. Let s move on to an example to illustrate relative addressing. We ve already seen this in the example of Simple Computer assembly language, but it won t hurt to look again. Assume that the subroutine do_something is located at memory location 0xff00, and we have to write a code fragment to call it 42 times. We ll need to write a loop to do it. To see the effect of relative addressing, we ll need to see the listing file, so here it is. Our code will be located starting at address 0xe000. ; Example code fragment to show how relative addressing ; works. The code is a loop to call a subroutine 42 ; times. org $e000 e ldaa #42 ; count down to 0 2a e loop: jsr do_something ff 00 e deca e006 2e bgt loop fa This should look familiar from the Simple Computer assembly code example, with the exception of the jsr instruction. The HC12 provides a good selection of conditional branches, for both signed and unsigned numbers. bgt is branch if the result of the last ALU operation is greater than zero. Look at the offset for the branch instruction in location 0xe007. Branch instructions use the relative addressing mode, with the PC playing the role 16

17 of the index register. We want to branch back to loop, so our target address is 0xe002. When the HC12 has finished fetching the instruction bgt loop, the PC will contain the value 0xe008 (the address of the next instruction following the bgt instruction, whatever that might be). We want an offset such that 0xe008 + offset = 0xe002. Rearranging, offset = 0xe002 0xe008 = 6 10 = 0xfffa. Truncated to eight bits, the proper offset is 0xfa. During the execution of the branch instruction, the HC12 will sign-extend the offset back to 16 bits before adding it to the PC to produce the effective address of the branch target. It s easy to forget that the PC already points to the next instruction when you re calculating the offset. Fortunately, the assembler will remember for you. The choice of a jsr ( jump subroutine) instruction to call do_something, instead of a bsr (branch subroutine) instruction, is determined by the address of do_something. do_something is located at address 0xff00, and 0xff00 0xe002 = 0x1efe = This exceeds the range for the 8-bit offset form of relative addressing and a check of the reference page for the bsr instruction shows that it does not support a 16-bit offset. jsr supports a wide range of addressing modes, including extended, the mode used here. At this point, it s natural to ask the question How do I find the right instruction? More generally, How do I plan out the implementation of an algorithm in assembly code? The first thing to do is to write down the algorithm, in pseudo-code or a programming language of your choice. Keep in mind that you re responsible for everything. There s no library of useful utilities, no support for complicated data structures. This is not the time to show off your knowledge of complex constructs supported by your favourite high-level language. Keep the pieces code and data structures small and simple. Build up gradually to complex functions. Now that you have some number of small, simple algorithms to implement, you can start thinking about instructions to implement them. 17

18 Make yourself familiar with the content of Chapter 5 of the CPU12 Reference Manual [2]. Don t try to memorise all those instruction groups! That s not the right way to approach this. The right way is to know (roughly) the capabilities of the various instruction groups, so that when you re writing your assembly code and you need to perform a particular action, you can narrow your search to one or two of the functional groups. If you need to move a value from one register to another, the first place to look is Table 5-2, Transfer and Exchange instructions. If you need to multiply a value by 2, you can consider one of the multiplication instructions (Table 5-10, Multiplication and Division), but maybe a simple left shift (Table 5-12, Shift and Rotate) will work just as well. If your algorithm requires a loop, check the capabilities of the Loop Primitive group in Table If there s nothing suitable there, look at the Increment and Decrement, Compare and Test, and Branch groups for the necessary functionality. Don t neglect Table A-1 in Appendix A. This is an excellent summary, in alphabetic order, and is a great place to look to see if an instruction supports a specific addressing mode, or to see how it affects the condition codes. As you start to consider different possibilities for instruction sequences, you ll realise that register usage, addressing mode, and choice of instructions are not independent. You must do them in parallel, and it will happen that you need to restructure the calculation because there s no instruction with just the right behaviour. Eventually, you ll need to know the details for a particular instruction. Does it support indexed addressing? What are the limits in terms of size of offset? To answer these questions you need to consult the reference pages in Chapter 6 of the CPU12 Reference Manual. Consider the page for the adda instruction, Add without Carry to A. At the top of the page, the operation performed by the instruction is specified in a register-transfer notation: (A) + (M) A In the notation used by the Reference Manual, parentheses ( ) mean contents of. The above expression says add the contents of register A to the contents of some memory location (to be determined by the addressing mode) 18

19 and put the result back in register A. See Chapter 1 of the Reference Manual for a complete explanation. Next comes a more human-friendly description which will also mention any interesting details. Following the Description is a block labelled CCR Details. Some instructions have no effect on the condition codes, while others set them according to the result of the operation. For adda the description is moderately complex. First is a compact symbolic representation: S X H I N Z V C The codes are given in 6.3; here, indicates no effect and indicates the bit is set appropriately for the operation. The exact details are given with boolean equations and text description. H: A3 M3 + M3 R3 + A3 R3 Set if there was a carry from bit 3; cleared otherwise. N: Set if MSB of result is set; cleared otherwise. Z: Set if result is $00; cleared otherwise. V: A7 M7 R7 + A7 M7 R7 Set if two s complement overflow resulted from the operation; cleared otherwise. C: A7 M7 + M7 R7 + A7 R7 Set if there was a carry from the MSB of the result; cleared otherwise. Unfortunately, a critical piece of explanation seems to have been lost in the transition from Motorola to Freescale. In these expressions, Rn refers to bit n in the result of the operation. Here, the result of the operation is the arithmetic sum. With a bit of boolean algebra, you can confirm that the boolean expressions are correct and match the text descriptions. Following the CCR Details section is a table showing the legal forms of the instruction: 19

20 Source Form Address Object Code Access Detail Mode HCS12 MHC12 ADDA #opr8i IMM 8B ii P P ADDA opr8a DIR 9B dd rpf rfp ADDA opr16a EXT BB hh ll rpo rop ADDA oprx0_xysp IDX AB xb rpf rfp ADDA oprx9, xysp IDX1 AB xb ff rpo rop ADDA oprx16, xysp IDX2 AB xb ee ff frpp frpp ADDA [D, xysp] [D, IDX] AB xb fifrpf fifrfp ADDA [oprx16, xysp] [IDX2] AB xb ee ff fiprpf fiprfp The information in this table is cryptic, but very informative once you re familiar with the codes. The Source Form column tells you how to write the instruction so that the assembler will recognise it. Elements in italic should be replaced with the appropriate numeric value or register specifier. The codes are explained in 6.5. The Address Mode column tells you the addressing mode that will be used, using the codes given in Table 3-1, Addressing Mode Summary. The remaining columns, Object Code and Access Detail, are not so interesting to us, but are important when you re trying to optimise your program for size, speed, or both. The Object Code column tells you how the instruction will be coded in machine language. Each code represents one byte; consult 6.4 for the meaning of each code. The information in the Access Detail column is primarily of interest to hardware designers who must design hardware that will interface with the HC12 core, or programmers who must accurately predict the execution speed of their program for real-time control applications. See 6.6 for the details. Note that each entry in the table represents one machine code representation. In particular, oprx0_xysp includes the addressing modes oprx5, xysp, abd, xysp, and the four autoincrement and autodecrement modes. All six are encoded as machine instructions using the same number of bytes. References [1] Freescale Semiconductor, Inc. HCS12 V1.5 Core User Guide Version 1.2, August [2] Freescale Semiconductor, Inc. CPU12 Reference Manual Rev. 4.0, March

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