Design of Transport Triggered Architecture Processor for Discrete Cosine Transform

Transcription

1 Design of Transport Triggered Architecture Processor for Discrete Cosine Transform by J. Heikkinen, J. Sertamo, T. Rautiainen,and J. Takala Presented by Aki Happonen

2 Table of Content Introduction Transport Triggered Architecture Move Framework ASIP for 32-point DCT Design Space Exploration Architecture Processor Generation Simulations Results Conclusions

3 Introduction Gap between productivity of designers and complexity of DSP applications Trend towards high level language and customizable architectures Customizable architectures enables tailoring according to the requirements of the application How to find satisfactory solution from large design space?

4 Transport Triggered Architecture (1/2) Transport Triggered Architecture (TTA) Program specifies only the data transports to be performed by the interconnection network Only one type of operation is supported move operation TTA processor consists: Functional units (FUs) With standard interface Used as basic building blocks Register files (RF) Containing general purpose registers Connected by interconnection network Connections to buses are established through input and output sockets Input socket: multiplexers feeding operands from buses to FUs Output socket: de-multiplexers placing the FU result into the correct bus

5 Transport Triggered Architecture (2/2) TTA processor architecture Can be tailored with special FUs without a need to change the transport capacity Illustrative block diagram of TTA FU = functional unit, RF =register file, LSU = Load store unit

6 MOVE Framework (1/2) MOVE framework is a design environment containing a set of SW tools for designing ASIPs (Application Specific Instruction-set Processors) Semi-automatic design process => Shorter design time Exploits scalability, flexibility, and simplicity of TTA Three principal components Design space explorer Search processor configuration to find the best cost/performance ratio HW resources of the processor are described in architecture description file Optimized HW resources first HW subsystem Generates the processor floorplan Commercial tools can be used for logic synthesis etc. SW subsystem Generates instruction level parallel code for chosen processor configuration

7 MOVE Framework (2/2) Illustrative figure of MOVE Framework

8 ASIP for 32-point DCT MOVE framework was used to generate ASIP for a 32- point DCT DCT used in an audio coding application The proposed DCT was described in C language Unrolled no iterations Fractional number representation was used Normalized into range [-1,1) 16 bits data words one bit for sign and 15 bits for magnitude ANSI C does not support that so normalization needed in multiplications was included as a shift of 15 bits

9 Design Space Exploration Design space explorer was used to find the optimal architecture configuration Set of configurations with local optimum Configuration with the best compromise between cost and performance was selected MOVE tools assume single memory space Each load store unit requires a port to the memory Three port memory would be required BUT used logic library supports only two port memories Third load store unit was omitted 26% increase in clock cycles Area and execution time estimations from design space explorer is based on cost model for 0.7um technology Targeted technology was 0.13um Performance comparison in terms of clock cycles rather than execution time

10 Architecture Optimized Architecture Configuration for 32-point DCT.

11 Processor Generation After processor configuration was found the structure of the processor can be defined MOVE framework contains processor generator to produce VHDL description of processor MOVE processor generator creates architecture with unnecessary features like cache and exception support Also MOVE compiler and processor generator contain some incompatibilities Manual modifications of VHDL code required To avoid manual modification a simple processor generator was developed to be compatible with the machine code generated by the MOVE compiler The generator combines manually written leaf cells (e.g. shifters, multipliers, ) and produces the necessary control logic and wires everything together at the top level Creates also scripts for logic synthesis, a test bench, and test vectors for RTL verification

12 Simulations MOVE SW subsystem was used to compile DCT application into an executable binary code for generated processor architecture Fairly large code size due to the long instruction word having dedicated slots to define data transports on each bus 46% of data transports are empty transports (NOP) Higher number of instructions Increase code size Entropy encoding proposed to code compression about 0.6 code compression ratio achieved

13 Total gate count: Standard cell area: 56k Macro cells: 34k Standard cell utilization: 78% Clock frequency: 250MHz for logic synthesis 350MHz without memory limitations Utilization: LSUs: 82% and 41% Three would have been better configuration as suggested by design space explorer ALUs: 48%, 37%, and 12% Three ALUs are sufficient Shifter: 27% Incorporate to multiplier Multiplier: 15% Low due the used DCT Results

14 Conclusions Due compatibility problems of the MOVE tools the result was not the most optimal solution for the DCT application Guard unit controlling the conditional execution was included even if it is not used since application was written totally unrolled Removing of guard unit would require changes in HW subsystem Guards always true => the guard fields could have been removed from the MOVE instructions Modifications to MOVE compiler Multiplier of the designed processor should include shifter Data buses available for other data transports Bus widths could be reduced To obtain more optimal processor the tools of MOVE framework would have been modified manually Not done due the focus was to evaluate the current status of MOVE tools