I 4 I I 1100 I I I -5 I 1011 I

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1 VLS DESGNS FOR REDUNDANT BNARY-CODED DEChOU ADDTON Behrooz Shirazi, David Y.Y. Yun, and Chang N. Zhang Department of Computer Science and Engineering Southern Methodist University Dallm. Tc-xas ABSTRACT Binary Coded Decimal (BCD) system provides rapid binary-decimal conversion. However, BCD arithmetic operations are often slow and require complex hardware [Chow 781. One can eliminate the need for carry propagation, and thus improve performance of BCD operations, through a Redundant Binary Coded Decimal (RBCD) system [Hwang 791. This paper introduces the VLS design of an RBCD adder. The design consists of two small PLA s and two 4- bit binary adders for one digit of the RBCD adder. The addition delay is constant for n-digit RBCD addition (no carry propagation delay). The VLS time and space complexities of the design as well as its layout are presented, showing the regularity of the structures. n addition, two simple algorithms and the corresponding hardware designs for conversion between RBCD and BCD are presented. ple algorithms and corresponding hardware designs for conversion between BCD and RBCD in both directions Finally, section 4 covers our concluding remarks. 2. VLS Deaigns for RBCD Addition A BCD digit is stored in 4 bits, which can represent 24 = 16 combinations. However, a BCD digit, ranging from 0 to 9, only uses ten of these combinations. Consider an RBCD representation with 15 digits, denoted by the set D = {-7, -6, -5, -4, -3, -1, 0, 1, 2, 3, 4, 5, 6, 7). Table 1 shows these digits and the corresponding RBCD codes. Note that the negation of a digit is its 2 s complement and representation of zero is unique. Table 1. RBCD digits. 1. ntroduction Decimal number system has proven to be one of the most natural number systems for human beings. Thus, numbers being input into a computer must first be converted from decimal to some binary representation. Conversely, binary-to-decimal conversion should be performed to output the numbers. n certain applications, a large number of such input/output conversions are required [Hayes 781. Therefore, it is important that number conversion be carried out rapidly. The Binary Coded Decimal (BCD) system allows very rapid binary-decimal conversion by encoding each decimal digit separately, using a sequence of 4 bits. However, BCD arithmetic operations are often complex and slow since they involve carry propagation [Chow 78, Hwang 791. n this paper we show that by using a Redundant Binary Coded Decimal (RBCD) system, we can still take advantage of rapid bin ary-decim al co nve rsions while improving the performance of arithmetic operations. Our goal is to provide hardware support for efficient BCD addition through an RBCD representation and carry save addition. Therefore, in this paper we introduce the design of an area/time efficient RBCD adder within the VLS technology constraints. We also discuss simple RBCD-to-BCD and vice versa conversions. n section 2, we present t,wo VLS designs for realization of RBCD addition. The time and space complexities of the designs are also discussed. Section 3 addresses two siin One can take advantage of carry save representatioi and carry save addition to eliminate carry propagation delay. in addition. Suppose we need to calculate the sum of two integers A and B ( A + B), where A and B are both in RBCD. Define a mapping F, F(A,B) = (C,S), such that A + B = C * 10 + S. Here, S is the sum and C is the carry to the next digit. Each digit of S is in a subset of D; namely, D = D - {-7, 7) == {-G, -5,..., 0,... 5, G}, and each digit of C is in the set (-1, 0, 1). Table 2 shows an addition table that satisfies the mapping F. The first and the second digits-of a table entry represent C and S, respectively. Digit d is the representation of -d in RBCD. We now discuss our attempts for the design of an efficient RBCD adder. Our first approach S very simple and straightforward with a high degree of regularity in the design. However, the system is slow and requires a large chip area. Therefore, we focused our efforts on a second approach which is a more complex design, but has better tiining and area requirements X/87/0000/0052$01.OO EEE 52

2 ..... Figun 1?be RED dder wilb U 's ud /D's. 2.1 First Approach: PLA Design The straightforward method to realize the addition Table 2 is to use the VLS Programmable Logic (PLA) technique: Let A = A inputs n-1 n-1 a, * 10' and B = b, * 10' where i-0 i-0 a;,bi ed= ( }. We wish to compute n S =A + B = si, si {-7,... 0,... 7). i-0 corresponding to the i-th digit of A, B, and S. From the RBCD addition table we can get the truth table depicted in Table 3, with 8 inputs and 6 outputs. represents a carry (ci = 1) to-the next digit (is.1-th), and indicates a borrow (ci = 1) to the next digit (i+l-th). Table 3. The truth table eorrrspondng b the RBCD rdditian table outputs B sum Cal" The addition time for n-digit integers is independent of the number of digits. t consist of the sum of the delay of a PLA and the delay of a 4-bit /D. The major disadvantage of this RBCD adder is the size of PLA's which is very large (the number of terms for a PLA is in excess of 200). This large PLA size also causes inefficiencies in terms of addition delay since the delay of a PLA is proportional to its area. For this reason, we chose a different approach for design of an RBCD adder, a5 explained in nextsub-section. 2.2 Second Approach: Binary Addition Let a = a3 U, u l a. and b = b3 6, b1 bo be RBCD representations of the two corresponding digits of A and B which are to be added. A close look at the RBCD addition Table 2 reveals that the major part of the table follows the rule of conventional binary addition; i.e. if -6<a+ b<6, we can use a 4-bit binary adder for adding (a) and (b). For the remaining cases, we can still use a binary adder for RBCD addition. However, the output of adder has to be corrected a5 follows: Case 1: The binary sum of the two digits of A and B is a member of {7,8,9,10,11,12,13,14}. Table 4 shows these cases along with the RBCD representations of the results. From this table it is clear that one can generate the corresponding RBCD digits from the binary sum (6) by adding 6 (denoted by f6) and sending a carry (denoted by to the next digit. For example, if the binary sum of two dkits is 9 (lool,), it can be corrected to get the RBCD digit l(1111,) by adding 6 (0110,) to it. w. 4. alsny- d m * ll0 4 etolw Let s = s3 s2 s1 so be the representation of the onedigit binary sum s. Then, j6 and fcsl conditions, which represent case 1, can be identified by: -- = (ss + s2 81 so) a3 b3. f6 = C-~ Case 2: The binary sum (s ) of the two digits of A and B is a member of {-7,-8,-9,-10,-11,-12,-13,-14}. Table 5 depicts these cases. Similar to case 1, the RBCD code can be obtained by adding -6 (denoted by and sending a 53

3 borrow (ci = 1 denoted by fc-i) to the next digit. These conditions can be detected by:... * ZOllllO?- 12 We can easily combine these two cases into one. For any pair of RBCD digits which are added by a binary adder, we either add 0, 6, or -6 depending on the binary sum and also add 0, 1, or -1 depending on the carry from the previous digit. Therefore, there are 9 possible numbers (-7, -6, -5, -1, 0, 1, 5, 6, 7) to add to the binary sum of two RBCD digits to correct the result. Let w = w3 w:, w1 wo be the binary number to be added to s to correct the sum. From the truth table of Table 6, we can get: ~3 = f,-ifs+ Jc w,=f-lf-6+f6 - - w1 E f$ /6 J,,i + 16 fc-i + fc-i fs = fc-i + fc-1. TaU. 8. 'Mh hble fc. bit. d ws.ws,wl,.nd wo l.e e Figure 2 presents the RBCD adder corresponding to the second approach. t consists of two small PLA's and two 4-bit binary adders. PLAl realizes fcnl, f,,~, fs, and f, and PLA2 generates wg, w2, wl, and wo. The first row of binary adders add the two RBCD digits. The two PLA's determine the correction amount, and finally, the last of row of binary adders correct the sum. Figure 2. The RBCD d dw eonsbb or \WO &bit ddtn and WO PLA'e. "inghalysis: The total delay of the RBCD adder shown in Figure 2 is the summation of the delays of PLA1, PLA2, and two 4-bit binary adders. t is noticeable that the RBCD addition delay is constant and independent of the input size. This can become very significant when large numbers are to be added. For simplicity in our timing analysis, we assume A to be the delay of an OR or AND gate with at most three inputs. Each of the two PLA's has a delay of 3Asince PLA 1 consists of 6 terms and PLA 2 consists of 5 terms. Consider the delay of one 4-bit binary adder. The delay of a 4-bit carry look-ahead adder is 6 4 calculated as follows: Let pi = xi + y, and gi = x;y, be the carry propagation and carry generation of the binary adder (x+y). The carrys (ci's) are c1 = 90, c2 = 91 ClP, = 91 SOP,, c3 = 92 + C2PZ = P2 + QOPlP2, and the sums (si's) are si = 5, + y; + ci. Thus, the delay of the 4-bit adder is 6 h The total delay of the RBCD adder is therefore, 18 Aregardless of number of digits. As a comparison, a conventional BCD adder, using carry look-ahead circuits, requires a delay of 7 n A for n digits. This is significantly greater than the delay of RBCD adder, especially for more number of digits. For example, a 50-digit BCD adder requires 350 A time delay which is about 20 times longer than the RBCD adder delay. Area Requirements: The VLS layout of a one-digit RBCD adder is shown in Figure 3. The geometry area is 1000x800 h2, where h is the resolution of nmos technology [Mead SO]. Due to time limitations, we did not consider optimized space utilization. However, it is noticeable that the chip area can be further improved by a better placement and routing strategy. Subtraction: Subtraction in RBCD is also much simpler and faster than BCD subtraction since there is no need to compute the 9's complement of a number. A-E can be carried out by getting 2's complement of each digit of B and adding the result to A. n fact, we have: 54

4 n-1 n-1 n-1 bi * 10' = (-bi) * 10'. A - B = ai * 10' - 0 ai * 10' + Table 7. BCD to RBCD connrsicm. 3( 1101) (1110) l(1111) - Therefore, given A = cai * lo', the conversion '-0 from BCD to RBCD can be done by the following two steps: For all 0 5 z 5 n-1 do step 1. ai = if gi = 0 ai if gi = 1' end. 0 if gi = 0 1 if gi = 1 step 2. ai if ci = 0 a. = { 1 ai+l if ci=l' Here, "and" represents parallelism between the two operations. For example, conversion of A = ( ) is ~ as ~ follows: ~ Ftyurc 3. YLS layout of the one-dlgit RBCD adder. 3. Conversions Between BCD and RBCD n previous section we introduced a VLS design for time-constant RBCD addition. However, the importance of BCD (or RBCD) representation is due to simple conversions between binary and BCD numbers. Therefore, RBCD arithmetic will not be of interest if we cannot easily and efficiently convert numbers to/from RBCD. n this section we present two efficient algorithms and their VLS design for conversion between BCD and RBCD. 3.1 BCD to RBCD Conversion Let (A) be the BCD number to be converted to n-1 RBCD. We have A = Ea' * lo', where ai E (0, 1, 0 2,..., 9)., (A) can be redefined as: A = E ai * 10' + ay * lo', where a! E {O,l,... 6} and af' E {7,8,9}. ':,is only necessary to convert the digits in the second part (ai E {7,8,9}) into the RBCD form. 9 dep icted in Table 7, an RBCD Pigit corresponding to ai can be generated by adding 6 to ai,, and rippling a carry to the next digit. These three cases (a. E {7,8,9}) can be identified by gi as gi = ah') + ai') a[') ah'), where a,(') is the jth bit of the ith BCD digit (J' = 0,1,2,3). step 1. step 2 ao=4, c, =O al = 8+6 = 14, c2 = 1 a2 = 9+6 = 15, c3 = 1 a,, =4 al = 14 = (~))RBCD a2 = =0 (carry to next digit) a3=o+1=1. Thus, (984)BCD=(1054))~BCD. Figure 4 shows the block diagram of the hardware required for BCD-to-RBCD conversion. The PLA realizes gi. Note that the conversion delay is again constant due to the fact that Steps 1 and 2 are simply digit-wise operations. For negative BCD numbers, we assume that a sign magnitude notation is used. n that case, the equivalent RBCD number can be easily obtained by converting the BCD digits to their equivalent RBCD and then getting 2's complemegt of each dig&. FQr example, -984 is first coverted to 1024 and then to RBCD to BCD Convension n-1 Given A = ai * lo', where ai ED = {-7, -6,... i }, leta = ati * 10' + ani * lo', where ati > 0 and a: 5 0. t is obvious that di is already in BCD form. Table 8 shows the cases of a: SO. Here, each BCD digit

5 can be obtained by-adding 8 to the corresponding RBCD digit and carrying a 1 to the next digit. This condition can be detected by hi = ~ 3. a, a,-]. 1 PLA Figure 4. Two digit conversion from BCD to RBCD. addition. Therefore, any carry look-ahead technique can be applied to speed up the rippling effect of /i's. 4. Conclusion This paper introduced an efficient design for a Redundant Binary-Coded Decimal adder. The proposed adder can perform RBCD addition in constant time, thus eliminating inefficiencies of conventional BCD addition. Two VLS designs for the RBCD adder were discussed. The first approach was a straightforward and simple implementation of the addition table using PLA's. However, the PLA size was very large, requiring long timing delays. The second approach used conventional 4-bit binary adders along with two small PLA's which were used to correct the final binary sum. The latter version required a small area with a minimal timing delay. The RBCD-BCD and BCD-RBCD conversions along with their hardware designs were discussed. These conversions can be considered as extensions of binary-decimal and decimal-binary conversions. BCD- RBCD conversion is carried out in constant time. RBCD- BCD conversion delay depends on number of digits, bu c.in be improved through a carry look-ahead technique. Table 8. RBCD to BCD amverim. RBCD BCD ai ai-] Notice that the digit zero has two equivalent mappings: first, it may map to 1010, (ten) with a borrow (-1) to the next digit, second, it may map to zero with no carry. The choice depends on the previous digit. f the previous digit is a positive integer or a zero which did not map into ten, then the zero remains as zero. Otherwise, the zero is mapped into ten and produces a borrow to the next digit. The latter condition can be identified by: Figure 5 presents the logic digram for RBCD-to-BCD conversion. PLAl generates f, and hi. PLA2 is similar to the PLA2 of the Figure 2. ts inputs are hi and fi-l and its outputs are sent to the 4-bit adder. The possible outputs of PLA2 are 0,-1,-6,-7. We can speed up the propagation of fi through a carry look-ahead technique. Let us redefine the terms in the logic formula for fi as: gi=aii), pi = TAi) Tii) Tii), and Cl = f l. Thus, we have fo=co =O and fi=c, = pi ci-l + gi. Obviously, this is the same iterative formula as the one used for carry representation in binary &bit adder J PL.49 Figure 5. Two digit conversion from RBCD to BCD. References [Chow 781. C. Y. Chow and J. E. Robertson "Logical Design of a Redundant Binary Adder" Proc. 4th symp. Comput. Arithmetic, pp , Oct [Hayes 781. J. P. Hayes, Computer Architecture and Organization, McGraw Hill, Hwang 791. K. Hwang, Computer Arithmetic/ Principles and Architecture and Design, John Wiley, Mead 801. C. A. Mead and L. A. Conway, ntroduction to VLSZ System, Addison-Wesley, Waser 821. S. Waser and M. J. Flynn, ntroduction to Arifhmetic for Digital Systems Designers, Holt, Rinehart and Winston, J 56

A Review of Various Adders for Fast ALU

58 JEST-M, Vol 3, Issue 2, July-214 A Review of Various Adders for Fast ALU 1Assistnat Profrssor Department of Electronics and Communication, Chandigarh University 2Assistnat Profrssor Department of Electronics