Vector Processing. Computer Organization Architectures for Embedded Computing. Friday, 13 December 13

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1 Vector Processing Computer Organization Architectures for Embedded Computing Friday, 13 December 13 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition, 2011, MK and from Prof. Mary Jane Irwin, PSU

2 Summary Previous class Thread-level Parallelism Today Vector Processors SIMD GPUs 2

3 Flynn s Classification Scheme SISD single instruction, single data stream aka uniprocessor: what we have covered until last class SIMD single instruction, multiple data streams single control unit broadcasting operations to multiple datapaths MISD multiple instruction, single data no such machine MIMD multiple instructions, multiple data streams aka multiprocessors (SMPs, MPPs, clusters, NOWs) Now obsolete terminology except for... 3

4 SIMD Processors Control Single control unit (one copy of the code) Multiple datapaths (Processing Elements s) running in parallel, executing the same instruction s are interconnected (usually via a mesh or torus) and exchange/share data as directed by the control unit Each performs the same operation on its own local data 4

5 Example SIMD Machines Maker Year # s # b/ Max memory (MB) clock (MHz) System BW (MB/s) Illiac IV UIUC ,560 DAP ICL , ,560 MPP Goodyear , ,480 CM-2 Thinking Machines , ,384 MP-1216 MasPar , ,000 Did SIMDs die out in the early 1990s?? 5

6 Multimedia SIMD Extensions The most widely used variation of SIMD is found in almost every microprocessor today Basis of MMX and SSE instructions added to improve the performance of multimedia programs A single, wide ALU is partitioned into many smaller ALUs that operate in parallel 8 bit 16 + bit 8 adder bit 32 + bit adder 816 bit bit + adder 8 bit + Loads and stores are simply as wide as the widest ALU, so the same data transfer can transfer one 32 bit value, two 16 bit values or four 8 bit values There are now hundreds of SSE instructions in the x86 to support multimedia operations 6

7 Vector processors: Vector Processors Highly-pipelined ALU, to get good performance at lower cost Set of vector registers to hold the operands and results Collect the data elements from memory Put them in order into a large set of registers Operate on them sequentially in registers Then write the results back to memory Formed the basis of supercomputers in the 1980 s and 90 s VMIPS: extending the MIPS instruction set to include vector instructions addv.d to add two double precision vector register values addvs.d and mulvs.d to add (or multiply) a scalar register to (by) each element in a vector register lv and sv do vector load and vector store and load or store an entire vector of double precision data 7

8 MIPS vs VMIPS DAXPY Codes: Y = a X + Y l.d $f0,a($sp) ;load scalar a addiu r4,$s0,#512 ;upper bound to load to loop: l.d $f2,0($s0) ;load X(i) mul.d $f2,$f2,$f0 ;a X(i) l.d $f4,0($s1) ;load Y(i) add.d $f4,$f4,$f2 ;a X(i) + Y(i) s.d $f4,0($s1) ;store into Y(i) addiu $s0,$s0,#8 ;increment X index addiu $s1,$s1,#8 ;increment Y index subu $t0,r4,$s0 ;compute bound bne $t0,$zero,loop ;check if done l.d $f0,a($sp) ;load scalar a lv $v1,0($s0) ;load vector X mulvs.d $v2,$v1,$f0 ;vector-scalar multiply lv $v3,0($s1) ;load vector Y addv.d $v4,$v2,$v3 ;add Y to a X sv $v4,0($s1) ;store vector result 8

9 Vector versus Scalar Instruction fetch and decode bandwidth is dramatically reduced (also saves power) Only six instructions in VMIPS versus almost 600 in MIPS for 64 element DAXPY Hardware doesn t have to check for data hazards within a vector instruction. A vector instruction will only stall for the first element, then subsequent elements will flow smoothly down the pipeline. And control hazards are nonexistent. MIPS stall frequency is about 64 times higher than VMIPS for DAXPY Easier to write code for data-level parallel applications Have a known access pattern to memory, so heavily interleaved memory banks work well. The cost of latency to memory is seen only once for the entire vector 9

10 The PS3 Cell Processor Architecture Composed of a non-smp architecture 234M 4Ghz 1 Power Processing Element (P) control processor. The P is similar to a Xenon core Slight ISA differences, and fine-grained MT instead of real SMT 8 Synergistic (SIMD) Processing Elements (Ss). The real compute power and differences lie in the Ss (21M transistors each) An attempt to fix the memory latency problem by giving each S complete control over it s own 256KB scratchpad memory 14M transistors Direct mapped for low latency 4 vector units per S, 1 of everything else 7M transistors 512KB L2$ and a massively high bandwidth (200GB/s) processor-memory bus 10

11 How to Make Use of the Ss 11

12 What about the Software? Uses special IBM Hypervisor Like an OS for OS s Runs both a real time OS (for sound) and non-real time OS (for things like AI) Software must be specially coded to run well The single P will be quickly bogged down Must make use of Ss wherever possible This isn t easy, by any standard What about Microsoft? Development suite identifies which 6 threads you re expected to run Four of them are DirectX based, and handled by the OS Only need to write two threads, functionally 12

13 History of GPUs Early video cards Frame buffer memory with address generation for video output 3D graphics processing Originally high-end computers (e.g., SGI) Moore s Law lower cost, higher density 3D graphics cards for PCs and game consoles Graphics Processing Units Processors oriented to 3D graphics tasks Vertex/pixel processing, shading, texture mapping, rasterization 13

14 Graphics in the System 14

15 GPU Architectures Processing is highly data-parallel GPUs are highly multithreaded Use thread switching to hide memory latency Less reliance on multi-level caches Graphics memory is wide and high-bandwidth Trend toward general purpose GPUs Heterogeneous CPU/GPU systems CPU for sequential code, GPU for parallel code Programming languages/apis DirectX, OpenGL C for Graphics (Cg), High Level Shader Language (HLSL) Compute Unified Device Architecture (CUDA) 15

16 Example: NVIDIA Tesla Streaming multiprocessor 8 Streaming processors 16

17 Example: NVIDIA Tesla Streaming Processors Single-precision FP and integer units Each SP is fine-grained multithreaded Warp: group of 32 threads Executed in parallel, SIMD style 8 SPs 4 clock cycles Hardware contexts for 24 warps Registers, PCs, 17

18 Classifying GPUs Don t fit nicely into SIMD/MIMD model Conditional execution in a thread allows an illusion of MIMD But with performance degradation Need to write general purpose code with care Instruction-Level Parallelism Data-Level Parallelism Static: Discovered at Compile Time VLIW SIMD or Vector Dynamic: Discovered at Runtime Superscalar Tesla Multiprocessor 18

19 GPGPU Programming Model General Purpose GPU (GPGPU) programming model reflects GPU hardware architecture: GPU seen as massively data parallel coprocessor large local memory CPU batches threads to the GPU, together with the data to process GPU threads extremely light-weight (little overhead) GPU requires 1,000s of threads for full efficiency 19

20 GPGPU Programming Difficulties Drawbacks of the GPGPU approach: Tough learning curve, particularly for those outside graphics Need to SIMD-ipify code Highly constrained memory layout and access model Need for many passes drives up bandwidth consumption 20

21 GPGPU Programming Example #include "cuda_runtime.h" #include "basic_timer.hpp" #include "idivup.hpp" #include "mini_cutil.h" #include <cmath> #include <cstdio> // calculates one exp per thread on the GPU. global void exp_kernel(float * v, int size) { int const t = threadidx.x + blockidx.x * blockdim.x; if (t < size) v[t] = exp(-(float)t) ; } int main(int argc, char * argv[]) { int n_elem = ; if (argc > 1) n_elem = atoi(argv[1]); // Allocate memory on the device float * vector_on_gpu = 0; cudaerror_t err = cudamalloc( &vector_on_gpu, n_elem*sizeof(float)); //... check error // Setup execution configuration dim3 block_size(256) ; // <-- how to pick this number? dim3 grid_size(idivup(n_elem, block_size.x)) ; // Launch the GPU computation. exp_kernel<<<grid_size, block_size>>>(vector_on_gpu, n_elem); // Wait for the GPU to finish. err = cudathreadsynchronize(); // check error... float *vector_on_cpu = (float*) malloc(n_elem*sizeof(float)); // Copy the results back to the CPU. err = cudamemcpy( (void*)vector_on_cpu, // destination on the CPU (void*)vector_on_gpu, // source on the GPU n_elem * sizeof(float), // copy size cudamemcpydevicetohost) ; // copy direction*/ cudafree((void*)vector_on_gpu) ; // Free the gpu memory // Now do the same on the cpu to compare times basic_timer timer ; for (int t = 0 ; t < n_elem ; ++t) vector_on_cpu[t] = exp(-(float)t) ; double elapsed = timer.elapsed() ; printf("cpu time %gs", elapsed) ; free(vector_on_cpu); } 21

22 Performance-Flexibility Curve RFORMANCE ASIC SCP FPGA ASIC: Application-Specific Integrated Circuit FPGA: Field-Programmable Gate Array DSP CPU FLEXIBILITY & TTM DSP: Digital Signal Processor CPU: Central Processing Unit SCP: Software Configurable Processor 22

23 Reconfigurable Co-Processors Standard processor coupled with embedded programmable logic where application specific functions are dynamically remapped depending on the performed algorithm 1: Coprocessor model 2: Function unit model 23

24 Application-Specific Processors (ASIPs) ASIP: Application-Specific Instruction-Set Processor Programmable processor optimized for a particular class of applications having common characteristics Compromise between general-purpose and ASIC (custom hardware) Features Program memory Optimized datapath Special functional units Benefits Some flexibility, good performance, size and power Examples DSPs, Video Signal Processors, Network Processors,.. Controller Control logic and State register IR PC Program memory Assembly code for: total = 0 for i =1 to Datapath Registers Custom ALU Data memory 24

25 Next Class Message Passing Multiprocessors (MPPs) Network topologies 25

26 Vector Processing Computer Organization Architectures for Embedded Computing Friday, 13 December 13 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition, 2011, MK and from Prof. Mary Jane Irwin, PSU

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