ELCT 912: Advanced Embedded Systems

Transcription

1 Advanced Embedded Systems Lecture 2: Memory and Programmable Logic Dr. Mohamed Abd El Ghany,

2 Memory Random Access Memory (RAM) Can be read and written Static Random Access Memory (SRAM) Data stored so long as v dd is applied 6-transistors per cell Faster Dynamic Random Access Memory (DRAM) Require periodic refresh Smaller (can be implemented by 1 or 3 transistors) slower Read-Only Memory (ROM) A memory device in which permanent binary information is stored Mask ROM: The programming is done by the semiconductor company during the last fabrication process of the unit PROM: Once the PROM is programmed, it cannot be reversed EPROM: An erasable PROM and can be erased by exposure to UV light EEPROM: Can be erased and programmed with electrical pulses Flash memory: High-density read/write memories that are nonvolatile. They have the ability to retain charge for years with no applied power 2

3 Block Diagram of Memory "#$ Example: 2MB memory, byte-addressable -N =8 (because of byte-addressability) -K= 21 (1 word= 8-bit)! 3

4 Static Random Access Memory (SRAM) % &% &% Typically each bit is implemented with 6 transistors (6T SRAM Cell) During read, the bitline and its inverse are precharged to Vdd (1) before set WL=1 During write, put the value on Bitline and its inverse on Bitline_bar before set WL=1 4

5 Dynamic Random Access Memory (DRAM) % & 1-transistor DRAM cell During a write, put value on bitline and then set WL=1 During a read, prechage bitline to Vdd (1) before assert WL to 1 Storage decays, thus requires periodic refreshing (read-sense-write) 5

6 Memory Description Capacity of a memory is described as # addresses x Word size 6

7 How to address Memory ( ) * "0 (, "# 0 * -. / ), ( 7

8 How to address Memory (1 ) * ( 1(, "0 "#0 *1 -. / ), ( ** 1(2 8

9 Use 2 Decoders "# 0 * ) * * "0 (, ( "0 * " * ( (, 3 & 9

10 Tristate Buffer 4 Could amplify signal Typically used for signal traveling e.g. bus $ $! "!0** 10

11 Bi-directional Bus using Tri-state Buffer * *! & 11

12 Read/Write Memory ) * ( *, "0 1( "# 0 * ( "0 * " * ( (, 12

13 Read/Write Memory ) * ( ( *, "0 1 "# 0 *1 ( "0 * " * ( (, 13

14 Building Memory in Hierarchy Design a 1Mx8 using 1Mx4 memory chips 2) "0 14

15 Building Memory in Hierarchy Design a 2Mx4 using 1Mx4 memory chips 5 6-2), ( "0 ( ( * "0 ( 5 6-2) ( "0 15

16 Building Memory in Hierarchy Design a 2Mx8 using 1Mx4 memory chips ( * ( ( ( 2) "0 2) "0 " ) ( " ) ( "0 16

17 Memory Model 32-bit address space can address up to 4 GB (2 32 ) different memory locations (2(((((((( (2((((((( (2((((((( (2( (2&. (2) % (2(((((((, (27" 89# ( (2( 7 17

18 Endianness [Danny Cohen 91] A byte ordering- How a multiple byte data word stored in memory Endianness (from Gulliver s Travels) Big Endian Most significant byte of a multi-byte word is stored at the lowest memory address E.g. Sun Sparc, PowerPC Little Endian Least significant byte of a multi-byte word is stored at the lowest memory address e.g. Intel x86 Some embedded & DSP processors would support both for interoperability 18

19 Endianness Examples Store 0x at address 0x0000 (2(((( (2((( (2((( (26- (2./ (2), % (2(((( (2((( (2((( (2 (2), (2./ % (2(((, (2 (2(((, (26- %33%$ $ 89# &:$ 89# 19

20 Read Only Memory (ROM) Permanent binary information is stored Non-volatile memory Power off does not erase information stored!! 20

21 32x8 ROM /, * (, 6 5,(,,26! 6 $*#, 7 * 21

22 Programming the 32x8 ROM!!!!!!!! " " " " " " " " " " " " " /, * ( 5,(, -. / ), ( 22

23 Example: Lookup Table Design a square lookup table for F(X)=X 2 using ROM # $%#&# # $%#&# 23

24 Square Lookup Table using ROM # $%#&#!!! (,6, * ) /. - " " " " " " 24

25 Square Lookup Table using ROM # $%#&#!!! (,6, * ) /. - " " " " " " $%& #! 25

26 Square Lookup Table using ROM # $%#&#!!!,6 (, * ) /. - " " " " " " 26

27 Classifying Three Basic PLDs ;3 ;3 72 * ;9 " * ;9! ;9!! ;9 ;9 " * ;9! ;9 %9*;%!3;3!3;3 ;3 ;9 72! ;9 %9*;% <* ;%= > ;%? *< 2 * * 7 7!3;3 27

28 Programmable Logic Array (PLA) ( ) **, (,* ( ) **, $(,* " 28

29 Example using PLA F1(A, B, C) = m(0,1,2,4) F2(A, B, C) = m(0,5,6,7) F1 = A B A C BC F1 = AB AC BC F2 = AB AC A BC 29

30 Example using PLA F1 F2 = = AB AB AC AC BC A B C & " &" &" " " 30

31 PLA Device ;9 ; 72!; 31

32 PLA Device Design Example & & " "!! 9 IO1 = AB C A BC D IO2 = AB C A BC D A C D A B CD 32

33 CPLD and FPGA [brown & Rose 96] Complex Programmable Logic Device (CPLD) Multiple PLDs (e.g. PALs, PLAs) with Programmable interconnection structure Pioneered by Altera Field-Programmable Gate Array (FPGA) High logic capacity with large distributed interconnection structure Logic capacity= number of 2-input NAND gates Offers more narrow logic resources CPLD offers logic resources with a wide number of inputs (AND planes) Offer a higher ratio of Flip-flops to logic resources than CPLD High Capacity PLD (HCPLD) is often used to refer to both CPLD and FPGA 33

34 CPLD Structure %9** ;% ;% ;% ;%!* * * ;% ;% ;% ;% 34

35 FPGA Structure %9**!* * * 35

36 FPGA Programmability Floating gate transistor Used in EPROM and EEPROM SRAM-controlled switch-control Pass transistors Multiplexers (to determine how to route inputs) Antifuse Similar to fuse Originally an Open-Circuit One-Time Programmable (OTP) 36

37 References Logic and Computer Design Fundamentals by M. Morris Mano and Charles R. Kime. 4th edition, Prentice Hall P. Marwedel: Embedded System Design, Springer, 2006 First Steps with Embedded Systems Byte Craft Limited 37