ECE 15B Computer Organization Spring 2011

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1 ECE 15B Computer Organization Spring 2011 Dmitri Strukov Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy,

2 Agenda Instruction formats Addressing modes Advanced dconcepts

3 Instruction formats

4 Simple datapath picture Let s add more details on this figure to see why instruction Let s add more details on this figure to see why instruction decoding could be simple and to see what is happening with for different instructions

High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,mips) Assembler

age Program (MIPS) Machine Interpretation Hardware Architecture Description (e.g., block

Below the Program temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $t0, 0($2) lw $t1, 4($2) sw

5 High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,mips) Assembler Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (e.g., block diagrams) Architecture Implementation Logic Circuit Description (Circuit Schematic Diagrams) Below the Program temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2)

6 One to one mapping Assembly instruction lw $t0, 0($2) Binary code One assembly instruction = 32 bit vector always 32 bits Macro or pseudo instruction > one line of code Examples: shift and rotate from Quiz 1 rol $a0, $a1, $a2 subu $t0, $0, $a2 srlv $t0, $a1, $t0 sllv $a0, $a1, $a2 or $a0, $a0, $t0

7 Datapath With Control

8 Instruction formats R format: op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I format: op rs rt constant or address 6 bits 5 bits 5 bits 16 bits J format: op address 6 bits 26 bits

9 R format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 note the order! (green card) special $s1 $s2 $t0 0 add =

10 R Type Instruction

11 Instruction formats R format: op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I format: op rs rt constant or address 6 bits 5 bits 5 bits 16 bits J format: op address 6 bits 26 bits

12 Load Instruction

13 Instruction formats R format: op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I format: op rs rt constant or address 6 bits 5 bits 5 bits 16 bits J format: op address 6 bits 26 bits

14 Target Addressing Example Loop code from earlier example Assume Loop at location Loop: sll $t1, $s3, add $t1, $t1, $s lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, j Loop Exit: 80024

15 Branch on Equal Instruction

16 MIPS PC relative or branch addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant oraddress 6 bits 5 bits 5 bits 16 bits PC relative addressing Target address = PC + offset 4 PC already incremented dby 4 by this time

17 Instruction formats R format: op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I format: op rs rt constant or address 6 bits 5 bits 5 bits 16 bits J format: op address 6 bits 26 bits

18 Target Addressing Example Loop code from earlier example Assume Loop at location Loop: sll $t1, $s3, add $t1, $t1, $s lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, j Loop Exit: 80024

19 Datapath With Jumps Added

20 Pseudodirect or Jump Addressing Jump (j and jal) targets could be anywhere in text segment Encode full address in instruction op address 6 bits 26 bits (Pseudo)Direct jump addressing Target address = PC : (address 4)

21 Implementing Jumps Jump 2 address 31:26 25:0 Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26 bit jump address 00 Need an extra control signal decoded from opcode

22 Branching Far Away If branch target is too far to encode with 16 bit offset, assembler rewrites the code Example beq $s0,$s1, L1 bne $s0,$s1, L2 j L1 L2:

23 Note on the PC incrementing Technical term for auto incrementation of PC is delayed branch By default in SPIM delayed branch is not checked. To see you SPIM settings look at simulator settings You can also check it by loading code to SPIM to check main : bne $s0, $s0, main

24 Loading constant values to registers Any immediate is 16 bit To load 32 bits constant one can use addi, sll + addi or better way to use lui rd, const (load upper immediate)

25 Specific Addressing Mode in MIPS

26 Various specific addressing modes in other ISAs Absolute address Immediate data Inherent address Register direct Register indirect Base register Register indirect with index register Register indirect with index register and displacement Register indirect with index register scaled Absolute address with index register Memory indirect Program counter relative

27 Example: Basic x86 Addressing Modes Two operands per instruction Source/dest operand Register Register Register Memory Memory Memory addressing modes Address inregister Address = R base + displacement Second source operand Register Immediate Memory Register Immediate Address = R + scale base 2 R index (scale = 0, 1, 2, or 3) Address = R base + 2 scale R index + displacement

28 Advanced Topics: Code density examples

29 Recent study (2009)

30 Code density examples

31 Advanced topics: Pipelining

32 Datapath With Control

33 Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance Four loads: Speedup = 8/3.5 = 2.3 Non stop: Speedup p = 2n/0.5n = number of stages

34 Pipeline registers Need registers between stages To hold information produced in previous cycle

35 Multi Cycle Pipeline Diagram Traditional form

36 Advanced topics: Cache design basics

37 Datapath With Control

38 Principle of Locality Programs access a small proportion popoto of their address space at any time Temporal locality Items accessed recently are likely to be accessed again soon e.g., instructions i in a loop, induction i variables ibl Spatial locality Items near those accessed recently entl are likely to be accessed soon E.g., g, sequential instruction access, array data

39 Taking Advantage of Locality Memory hierarchy Store everything on disk Copy recently accessed (and nearby) b)items from disk to smaller DRAM memory Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory Cache memory attached to CPU

40 Direct Mapped Cache Location determined by address Direct mapped: only one choice (Block address) modulo (#Blocks in cache) #Blocks is a power of 2 Use low order address bits

41 Tags and Valid Bits How do we know which particular block is stored in a cache location? Store block address as well as the data Actually, only need the high order bits Called the tag What if there is no data in a location? Valid bit: 1 = present, 0 = not present Initially 0

42 Example: Direct mapped cache

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations