Programming Languages

Transcription

1 Programming Languages Dr. Michael Petter Exam First Name Surname Student ID Signature Fill out the fields above. Make use only of an indelible pen in black or blue color. Do not make use of Tipp-Ex or something similar. To solve the exam you have 90 minutes. Check that you received 10 pages. The maximum number of points that you can obtain in this exam is 40. You need 16 points to pass. One annotated double-sided A4 sheet is permitted Σ 1

2 Assignment 1 MESI [8 Points] In this assignment, we assume a Hardware Model with caches and store buffers. Consider the following initialization code, with int a[4] s values being initally zero: i=1; t=1; a[0]=1; Next, ths P 0 and P 1 are spawned: Th P 0 : Th P 1 : while(i<4){ while(i<4){ // A (i<4) && (t==1) if (t==0) { if (t==1) { a[i]=a[i-1]*2; a[i]=a[i-1]*2; i++; i++; t=1; t=0; } } } } 1. [1P] Fill in the gap with either will, will never or may or may not : Th P 1 will terminate. 2. [1P] There is at least one execution of the program, in which th P 0 accesses array a out of bounds. (a) [1P] Provide a configuration (i.e. cache states, variable values, reachable from program start) of the machine passing the program point marked with the comment A, which fullfills the annotated conditions, yet may ultimately lead to P 0 trying to write to a[4]. (b) [6P] Provide an interleaving of instructions of the run from comment A on your configuration to the actual array access out of bounds. Draw the sequence diagram! 2

3 Solution 1 2. (a) i=3s, t=1s, a[0]=1s,a[1]=2s,a[2]=4s,a[3]=0s (b) P 1 (t==1) a[2]*2 a[3]=... i++ t=0 P 0 (i<4) (t==0) a[3]*2 a[4]=... P 1 t i a[2] a[3] sbuff sbuff [ ] a[3] S0 i S3 t S1 (t==1) S1 S3 S4 S0 [ ] (c) a[i-1]*2 a[i]=... i++ t=0 M8 [ a[3]=8 ][ a[3]=8,i=4 [ a[3]=8 ] ] invalidate inv ack I I I M0S0 M4 S4 write back S0 write back write back S4 S8 S8 > time P 0 (i<4) 1P interleaving 1P cascade in P 1 1P write cascade in P 1 going to SB 1P invalidate P 0 & propagate writes to cache 1P /write back cascade 1P ing outdated i and actual i Subtractions for don ts -1P for ignored sbuff -1P for ignored i-accesses -1P for ignored messages -1P for ignored states -1P for ignored initial states (t==0) a[i-1]+2 a[i]=... 3

4 Assignment 2 Transactional Memory [8 Points] In this assignment, we assume a hardware model with caches and Restricted Transactional Memory, but without storebuffers or invalidation buffers. Consider the following initialization code with int a[6] s values being initally zero: a[0]=1; a[1]=1; a[2]=2; Next, ths P 3... P 5 and R 3... R 5 are spawned: Th P i : while(_xbegin()==1){ if(a[i-1]*a[i-2]==0) _xabort(); a[i]=a[i-1]+a[i-2]; _xend(); } Th R i : while(_xbegin()==1){ if(a[i-2]*a[i-3]==0) _xabort(); a[i]=2*a[i-2]+a[i-3]; _xend(); } 1. [1P] Fill in the gap with either will, will not or may or may not : Given enough time, all P i and R i will terminate. 2. [1P] Fill in the gap with either exactly once, exactly twice or once or twice : Given enough time, some value will be stored to the memory address of a[i] with i {3,..., 5} exactly twice. 3. [1P] Fill in the gap with either All sequences, There exists a sequence or There is no sequence : There exists a sequence of executions such that ths P i and P j with i j terminate without ever aborting. 4. [5P] Consider the following interleaving of ths P i and R j : P i _xbegin()==1 (a[i-1]*a[i-2]==0) a[i-1]+a[i-2] a[i]=... _xend() R j _xbegin()==1 (a[j-2]*a[j-3]==0) 2*a[j-2]+a[j-3] a[j]=... _xend() > time (a) [1P] Choose a value for i and j resp., such that this interleaving is possible. (b) [4P] Draw a happened-before diagram of this interleaving. You can assume i and j to reside in registers, i.e. they do not need to be modeled in cache. The initial cache states for all a[*] are invalid. 4

5 Solution 2 4. (a) i=3, j=4 _xbegin()==1 P a[1] 3 I a[2] I a[3] I (b) (a[2]*a[1]==0) a[2]+a[1] a[3]=... _xend() TE1 TS1 S1 TE2 TS2 S2 TM3 M3 mem resp. resp. resp. resp. inv. resp. inv. resp. a[4] I a[2] I a[1] I TS1 TS2 TM5 M5 S2 S1 R 4 _xbegin()==1 (a[2]*a[1]==0) 2*a[2]+a[1] a[4]=... _xend() 1P Transaction opened exclusive in P 3 1P TS? in both 1P local computation 1P Transaction commit in both 5

6 Assignment 3 Dispatching Consider the following Java code: [8 Points] public class A { public static void p(object o) { System.out.print(o+" ");} public A func(a a) { p("a.func(a)"); return a; } public A proc(b b) { func(b); return b; } public A meth(b b) { b.func(this); return b; } public A trai(a a) { p("a.trai(a)"); return a; } } public class B extends A implements V { public A func(b b) { p("b.func(b)"); return b; } public A func(a a) { p("b.func(a)"); return a; } } public interface V { public default A trai(a a) { A.p("V.trai(A)"); return a; } } Provide the console output for the following statements: 1. B b = new B(); A a = b; a.func(a); B.func(A) 2. B b = new B(); A a = b; b.func(b); B.func(B) 3. B b = new B(); A a = b; a.func(b); B.func(A) 4. B b = new B(); A a = b; b.proc(b); B.func(A) 5. B b = new B(); A a = b; b.meth(b); B.func(A) 6. B b = new B(); A a = b; b.func(a).func(b); B.func(A) B.func(A) 7. B b = new B(); A a = b; b.trai(b); A.trai(A) 8. B b = new B(); V v = b; v.trai(b); A.trai(A) 6

7 Assignment 4 Multiple Inheritance [8 Points] 1. [3P] Consider the following C++ class definitions: class A { public: int a; virtual void f(); } class B : public A { public: int b; virtual void f(); } class C : public A, public B { public: int c; virtual void f(); } Draw a memory representation diagram for a C-Object, and the virtual table for class C! 2. [3P] Consider the following C++ Class Definitions: class A { public: int a; virtual void f(); } class B : public virtual A { public: int b; virtual void f(); } class C : public B, public A { public: int c; virtual void f(); } Draw a memory representation diagram for a C-Object, and the virtual table for class C! 3. [2P] Extend the C++ Class hierarchy from assignment 4.2, such that the offset between the memory representation of class B and its virtual base A differs from the offset in assignment 4.2! Draw a memory representation diagram for your class-hierarchy! 7

8 Solution 4 1. B { B int b C int c 0 C::f() B C::Bf() 1P correct composition 1P correct s/subtables (incl.offset-to-top) 1P correct function pointers (incl. thunk marker) -1P forgotten 2nd A A1{ A2{ B int b C int c A2 0 C::f() A1 C::AinCf() A2 A2 2. C::AinBf() 1P correct composition 1P correct s/subtables (incl.offset-to-top & vbase-ptr) 1P correct function pointers (incl. vcall-offset, thunk marker) 3. class A { public: int a; virtual void f(); } class B : public virtual A { public: int b; virtual void f(); } class C : public B, public A { public: int c; virtual void f(); } class D : public C { public: int d; } A1{ A2{ B int b C int c D int d 1P correct extension of class specification 1P correct compostion idea 8

9 Assignment 5 Stream Wrapper Mixin with Prototypes Consider the following Lua code: [8 Points] Stream = {} Stream. index = Stream function Stream:write(character) function Stream:new(object) setmetatable(object,self) return object end Mutex = {} Mutex. index = Mutex function Mutex:lock()... end function Mutex:unlock()... end function Mutex:new() object = {} setmetatable(object,self) return object end... end 1. [4P] Create a memory diagram after execution of the code above together with: mystream = Stream:new({ mutex = Mutex:new() }) 2. [4P] Extend the program by a creator function. This function should produce a wrapper table for tables, that were created with Stream:new. More specifically, this wrapper table should delegate every lookup to the wrapped table, with one exception: in case, the function write is called, the new table should establish a Mutex-locked area around a call to the wrapped table s original write function. 9

10 Solution 5 Stream mystream index write new Stream 0x??? 0x??? Mutex index unlock lock Mutex 0x??? 0x??? meta Stream anonym new 0x??? mutex meta Mutex function creator(stream) local Wrapper = { mutex = Mutex:new() } setmetatable(wrapper,stream) function Wrapper:write(character) self.mutex:lock() getmetatable(self). index:write(character) self.mutex:unlock() end return Wrapper end 1P return a new table with a mutex for each stream 1P overwrite write with custom mutex access 1P call ancestor 1P delegate all else to ancestor 10