361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control

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1 36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control

2 Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 26 2 op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: 3 26 j target op target address 6 bits 26 bits 36 control.2

3 Recap: A Single Cycle Datapath We have everything ecept control signals (underline) RegDst Today s lecture will show you how to generate the control signals busw RegWr imm Rw Ra Rb -bit Registers 6 busb Etender Branch Jump busa ALUSrc Instruction Fetch Unit ALUctr Data In ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr Adr Data Memory <:5> <:5> Imm6 MemtoReg 36 control.3 EtOp

4 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory Input Datapath Output Today s Topic: Designing the Control for the Single Cycle Datapath 36 control.4

5 Outline of Today s Lecture Recap and Introduction Control for Register-Register & Or Immediate instructions Control signals for Load, Store, Branch, & Jump Building a local controller: ALU Control The main controller Summary 36 control.5

6 RTL: The ADD Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the net instruction s address 36 control.6

7 Instruction Fetch Unit at the Beginning of Add / Subtract Fetch the instruction from Instruction memory: Instruction <- mem[pc] This is the same for all instructions PC<3:28> Target Instruction<25:> Addr<3:2> Addr<:> Instruction Memory PC 3 imm6 Instruction<5:> 6 Adder SignEt 3 Adder 3 3 Jump = previous Instruction<3:> Branch = previous Zero = previous 36 control.7

8 The Single Cycle Datapath during Add and Subtract 3 26 R[rd] <- R[rs] + / - R[rt] RegDst = busw RegWr = 2 6 op rs rt rd shamt funct imm Rw Ra Rb -bit Registers 6 Branch = Jump = busb Etender busa ALUctr = Add or Subtract Data In ALUSrc = Instruction Fetch Unit ALU Zero 6 Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> <:5> Imm6 MemtoReg = 36 control.8 EtOp =

9 Instruction Fetch Unit at the End of Add and Subtract PC <- PC + 4 This is the same for all instructions ecept: Branch and Jump PC<3:28> Target Instruction<25:> Addr<3:2> Addr<:> Instruction Memory PC 3 imm6 Instruction<5:> 6 Adder SignEt 3 Adder 3 3 Jump = Instruction<3:> Branch = Zero = 36 control.9

10 The Single Cycle Datapath during Or Immediate op rs rt immediate R[rt] <- R[rs] or ZeroEt[Imm6] RegDst = busw RegWr = imm Rw Ra Rb -bit Registers 6 Branch = Jump = busb Etender busa 6 ALUctr = Or ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> <:5> Imm6 MemtoReg = 36 control. EtOp =

11 The Single Cycle Datapath during Or Immediate op rs rt immediate R[rt] <- R[rs] or ZeroEt[Imm6] RegDst = busw RegWr = imm Rw Ra Rb -bit Registers 6 busb Etender npc_sel= +4 busa 6 ALUctr = Or ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> <:5> Imm6 MemtoReg = 36 control. EtOp =

12 The Single Cycle Datapath during Load op rs rt immediate R[rt] <- Data Memory {R[rs] + SignEt[imm6]} RegDst = RegWr = busw imm Rw Ra Rb -bit Registers 6 Branch = Jump = busb Etender busa ALUSrc = Instruction Fetch Unit ALUctr = Add Data In ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> Imm6 MemtoReg = <:5> 36 control.2 EtOp =

13 The Single Cycle Datapath during Load op rs rt immediate R[rt] <- Data Memory {R[rs] + SignEt[imm6]} RegDst = RegWr = busw imm Rw Ra Rb -bit Registers 6 busb Etender npc_sel= +4 busa ALUctr = Add ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> Imm6 MemtoReg = <:5> 36 control.3 EtOp =

14 The Single Cycle Datapath during Store op rs rt immediate Data Memory {R[rs] + SignEt[imm6]} <- R[rt] RegDst = RegWr = busw imm Rw Ra Rb -bit Registers 6 Branch = Jump = busb Etender busa ALUctr = Add Data In ALUSrc = Instruction Fetch Unit ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> <:5> Imm6 MemtoReg = 36 control.4 EtOp =

15 The Single Cycle Datapath during Store op rs rt immediate Data Memory {R[rs] + SignEt[imm6]} <- R[rt] RegDst = RegWr = busw imm Rw Ra Rb -bit Registers 6 busb Etender npc_sel= +4 busa ALUctr = Add Data In ALUSrc = Instruction Fetch Unit ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemtoReg = MemWr = Adr Data Memory <:5> <:5> Imm6 36 control.5 EtOp =

16 The Single Cycle Datapath during Branch op rs rt immediate if (R[rs] - R[rt] == ) then Zero <- ; else Zero <- RegDst = RegWr = busw imm Rw Ra Rb -bit Registers 6 Branch = Jump = busb Etender busa ALUSrc = Instruction Fetch Unit ALUctr = Subtract Data In ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> <:5> Imm6 MemtoReg = 36 control.6 EtOp =

17 Instruction Fetch Unit at the End of Branch op rs rt immediate 6 if (Zero == ) then PC = PC SignEt[imm6]*4 ; else PC = PC + 4 PC 3 imm6 Instruction<5:> 6 PC<3:28> Target Instruction<25:> Adder SignEt Adder Branch = Zero = Jump = Assume Zero = to see the interesting case. Addr<3:2> Addr<:> Instruction Memory Instruction<3:> 36 control.7

18 Instruction Fetch Unit at the End of Branch op rs rt immediate 6 if (Zero == ) then PC = PC SignEt[imm6]*4 ; else PC = PC + 4 Inst Memory Adr Instruction<3:> npc_sel 4 Adder PC 36 control.8 imm6 Adder

19 The Single Cycle Datapath during Jump 3 26 op target address Nothing to do! Make sure control signals are set correctly! RegDst = RegWr = busw imm Rw Ra Rb -bit Registers 6 Branch = Jump = busb Etender busa ALUctr = Data In ALUSrc = Instruction Fetch Unit ALU Zero Instruction<3:> <2:25> WrEn <6:2> MemWr = Adr Data Memory <:5> <:5> Imm6 MemtoReg = 36 control.9 EtOp =

20 Instruction Fetch Unit at the End of Jump 3 26 op target address PC <- PC<3:29> concat target<25:> concat PC<3:28> Target Instruction<25:> Addr<3:2> Addr<:> Instruction Memory PC 3 imm6 Instruction<5:> 6 Adder SignEt 3 Adder 3 3 Jump = Instruction<3:> Branch = Zero = 36 control.2

21 Step 4: Given Datapath: RTL -> Control Instruction<3:> Inst Memory Adr Op <2:25> Fun <2:25> <:5> <:5> <6:2> Imm6 Control npc_selregwr RegDst EtOp ALUSrc ALUctr MemWr MemtoReg Equal DATA PATH 36 control.2

22 A Summary of Control Signals inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, npc_sel = +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = sub, RegDst = rd, RegWr, npc_sel = +4 ORi R[rt] < R[rs] + zero_et(imm6); PC < PC + 4 ALUsrc = Im, Etop = Z, ALUctr = or, RegDst = rt, RegWr, npc_sel = +4 LOAD R[rt] < MEM[ R[rs] + sign_et(imm6)]; PC < PC + 4 ALUsrc = Im, Etop = Sn, ALUctr = add, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_et(imm6)] < R[rs]; PC < PC + 4 ALUsrc = Im, Etop = Sn, ALUctr = add, MemWr, npc_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign_et(imm6)] else PC < PC + 4 npc_sel = Br, ALUctr = sub 36 control.22

23 A Summary of the Control Signals See func We Don t Care :-) Appendi A op add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUctr<2:> Add Subtract Or Add Add Subtract R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump 36 control.23

24 The Concept of Local Decoding op R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUop<N:> R-type Or Add Add Subtract op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 ALU 36 control.24

25 The Encoding of ALUop op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 In this eercise, ALUop has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, ALUop hat to be 3 bits to represent: () R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, (4) Subtract, and (5) And (Eample: andi) ALUop (Symbolic) ALUop<2:> R-type ori lw sw beq jump R-type Or Add Add Subtract 36 control.25

26 The Decoding of the func Field op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 R-type ori lw sw beq jump ALUop (Symbolic) R-type Or Add Add Subtract ALUop<2:> R-type op rs rt rd shamt funct ( P. 286 tet) funct<5:> Instruction Operation add subtract and or set-on-less-than ALUctr ALU ALUctr<2:> ALU Operation Add Subtract And Or Set-on-less-than 36 control.26

27 The Truth Table for ALUctr ALUop R-type ori lw sw beq (Symbolic) R-type Or Add Add Subtract ALUop<2:> funct<3:> Instruction Op. add subtract and or set-on-less-than ALUop bit<2> bit<> bit<> bit<3> func bit<2> bit<> bit<> ALU Operation ALUctr bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Set on < 36 control.27

28 The Logic Equation for ALUctr<2> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<2> X Y Z A B C D This makes func<3> a don t care ALUctr<2> =!ALUop<2> & ALUop<> + ALUop<2> &!func<2> & func<> &!func<> =!X&Y + X&!A&!B&C&!D + X&A&!B&C&!D =!X&Y + X&!B&C&!D 36 control.28

29 The Logic Equation for ALUctr<> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<> ALUctr<> =!ALUop<2> &!ALUop<> + ALUop<2> &!func<2> &!func<> 36 control.29

30 The Logic Equation for ALUctr<> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<> ALUctr<> =!ALUop<2> & ALUop<> + ALUop<2> &!func<3> & func<2> &!func<> & func<> + ALUop<2> & func<3> &!func<2> & func<> &!func<> 36 control.3

31 The ALU Control Block func 6 ALUop 3 ALU Control (Local) ALUctr 3 ALUctr<2> =!ALUop<2> & ALUop<> + ALUop<2> &!func<2> & func<> &!func<> ALUctr<> =!ALUop<2> &!ALUop<> + ALUop<2> &!func<2> &!func<> ALUctr<> =!ALUop<2> & ALUop<> + ALUop<2> &!func<3> & func<2> &!func<> & func<> + ALUop<2> & func<3> &!func<2> & func<> &!func<> 36 control.3

32 Step 5: Logic for each control signal npc_sel <= if (OP == BEQ) then EQUAL else ALUsrc <= if (OP == ype ) then regb else immed ALUctr <= if (OP == ype ) then funct elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add EtOp <= MemWr <= MemtoReg <= RegWr: <= RegDst: <= 36 control.

33 Step 5: Logic for each control signal npc_sel <= if (OP == BEQ) then EQUAL else ALUsrc <= if (OP == ype ) then regb else immed ALUctr <= if (OP == ype ) then funct elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add EtOp <= if (OP == ORi) then zero else sign MemWr <= (OP == Store) MemtoReg <= (OP == Load) RegWr: <= if ((OP == Store) (OP == BEQ)) then else RegDst: <= if ((OP == Load) (OP == ORi)) then else 36 control.33

34 The Truth Table for the Main Control op 6 Main Control RegDst ALUSrc : ALUop 3 func 6 ALU Control (Local) ALUctr 3 36 control.34 op R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUop (Symbolic) R-type Or Add Add Subtract ALUop <2> ALUop <> ALUop <>

35 The Truth Table for RegWrite op R-type ori lw sw beq jump RegWrite RegWrite = R-type + ori + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) op<5>.. op<> op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> R-type ori lw sw beq jump RegWrite 36 control.35

36 PLA Implementation of the Main Control op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump EtOp ALUop<2> ALUop<> ALUop<> 36 control.36

37 op 6 Instr<3:26> RegDst Putting it All Together: A Single Cycle Processor busw Main Control RegWr imm6 Instr<5:> Rw Ra Rb -bit Registers 6 ALUop RegDst ALUSrc : busb Etender Branch Jump busa 3 ALUSrc Instruction Fetch Unit ALUctr func Instr<5:> 6 Data In ALU Zero Instruction<3:> ALU Control <2:25> WrEn <6:2> MemWr Adr Data Memory ALUctr <:5> 3 <:5> Imm6 MemtoReg 36 control.37 EtOp

38 Clocking Methodology Setup Hold Don t Care Setup Hold All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time 36 control.38

39 Worst Case Timing (Load) PC,,, Op, Func ALUctr Old Value -to-q New Value Old Value Old Value Instruction Memoey Access Time New Value Delay through Control Logic New Value EtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value busa busb 36 control.39 Old Value Delay through Etender & Old Value Register Write Occurs Register File Access Time New Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busw Old Value New

40 Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time is much longer than needed for all other instructions 36 control.4

41 36 control.4 Summary Single cycle datapath => CPI=, CCT => long 5 steps to design a processor. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Control is the hard part MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Processor Control Datapath Memory Input Output

EEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control

EEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC