Computer Hardware Engineering

Transcription

1 2 Coue Structure Computer Hardware Engineering IS2, spring 2 Lecture : LU and s Module : I/O Systems Module : Logic Design L DCÖ L DCÖ2 Lab:dicom L7 Module 2: C and ssembly Programming ssociate Professor, KTH Royal itute of Technology L L2 ssistant Research Engineer, Univeity of California, Berkeley L E2 L E Slides veion. Revision v., June 7, 2: Minor fix in the figures on slides 2 and 22. L6 Lab: nios2io E9 Lab: nios2int L8 Home Lab: cache E8 Lab: nios2time Home lab: C Module 6: Parallel Processo and Programs Module : Processor Design L E7 Module : Hierarchy E E E6 E L9 L E I bstractions in Computer Systems Computer System genda etworked Systems and Systems of Systems pplication Software Software Operating System Set rchitecture Hardware/Software Interface Microarchitecture Logic and Building Blocks Digital Hardware Design Digital Circuits I nalog Circuits Devices and Physics nalog Design and Physics I I

2 6 (LU) cknowledgement: The structure and several of the good examples are derived from the book Digital Design and Computer rchitecture (2) by D. M. Harris and S. L. Harris. n LU saves hardware by combining different arithmetic and logic erations in one single unit/element. LU Y B F F LU LU symbol: both figures have the same function B Y Input F specifies the function that the LU should perform LUs can have different functions and be designed differently. n LU can also include output flags, for instance: Overflow flag (adder overflowed) Zero flag (output is zero) I I (LU) H E 7 8 F 2 B Exercise: Determine the functional behavior for each value of F. Most significant bit (number 2) Bits to [-] Zero Extend Extract the most significant bit 2 F : Y F 2: dd zeros from bit - to. Function D B OR B B not used D!B OR!B B SLT I cknowledgement: The structure and several of the good examples are derived from the book Digital Design and Computer rchitecture (2) by D. M. Harris and S. L. Harris. I

3 9 s Path and Control Unit In this lecture, we construct a microarchitecture for a subset of a MIPS processor with the following instructions processor is typically divided into two pas R-Type: add, sub, and, or, slt Path Operates on a word of data. Consists of elements such as registe, memory, LUs etc. / logic instructions instructions I-Type: ediate instruction J-Type: I The architectural states for this MIPS processor are the program counter () and the registe ($, $t, $s, $s, etc.) -bit address results in 2 = registe at the next clock cycle at the current clock cycle next Program Counter () -bit register j Reads -bit word of data -bit address 2 2 registe of size -bit simplified instruction memory, modeled as a read-only memory (ROM) Two read pos ( and 2) and one write po (). I -bit address 2 Writes on the rising clock edge and when write enable () is true I State Elements (2/2) s and Memories Reads -bit data State Elements (/2) Program Counter and Register File Branch instructions addi, lw, sw, beq Control Unit Gets the current instruction from the data path and tells the data path how to execute the instruction. Reads or writes -bit word of data onarchitectural states are used to simply logic or increase performance (introduced in next lecture). I

4 Read from the Current lw instruction Read Base ddress next bits bits Read out the base address from the register file. 2:2 cuts out the from the instruction. Example lw $s,($s) Base address in has now the address stored in $s (in the above example). Fit step. Read the instruction at the current address. -bit instruction r is fetched. next 2:2 2 2 I I 6 lw instruction Read Offset lw instruction Read Word bits next 2 2 The offset is found in the least significant 6 bits of the instruction. 6 : 2:2 2 6 bits 2 S Example lw $s,($s) The offset is stored in the field. The offset is signed. Sign extend to bits. That is: S : = : S :6 = next The base address and the offset are added together : 2:2 2 2 Control code for S 2 LU Example lw $s,($s) Reads out the data word from data memory. I I

5 7 8 lw instruction Write Back lw instruction Increment 26 2 next 2 2 Reads out of the register to enable write back of result. : 6 2:2 2 2:6 2 Write enable S 2 LU Example lw $s,($s) Write back the result next : 2:2 2 2:6 2 Increment the by. (ext instruction is at address ) S 2 LU This is the complete data path for the load word (lw) instruction. I I 9 2 sw instruction Increment We need to read the base address, read the offset, and compute an address. Good news: We have already done that!. next The word to be stored is saved in a register (-field in the I-type) : 2:2 2:6 2 2:6 2 Write enable must be false S 2 LU Example sw $s,($s) The data word is stored into the memory R-type instructions Machine Encoding We are now going to handle all R-type instructions the same uniform way. That is, we should handle add, sub, and, or, and slt. I-Type R-Type bits bits bits The and fields are in the same place for both I-Type and R-Type rd shamt 6 funct 6 bits I I

6 2 22 R-type instructions LU Usage R-type instructions Write to Register We want to send the second erand to the LU, but still be compatible with the lw-instruction. Different LU control signals for different instructions. R-Type instructions write to registe and not to memory. Bypass the data memory if an R-Type instruction next : 2:2 2:6 2 : 2 S LUSrc = LUControl MemWrite = LU next : 2:2 2:6 2 : 2 S LUSrc = LUControl LU MemWrite = MemToReg = I I 2 2 I-Type R-Type R-type instructions Machine Encoding bits bits bits For the lw instruction, the target register is stored in the field (bits 2:6) For R-type instructions, the target register is stored in the rd field (bits :) rd shamt funct 6 bits 6 next R-type instructions Use the rd field Write to register using rd field instead of. 2:2 2:6 2 : RegWrite = 2 RegDst = LUSrc = 2:6 : LUControl LU Create a control variable for register write. MemWrite = MemToReg = I I

7 2 26 beq instruction Machine Encoding beq instruction Compare if equal Recall that the beq instruction is a branch instruction, encoded in the I-Type. I-Type bits The and fields specify the registe that should be compared. Recall how to compute the BT: BT = * 6 bits The field is used when computing the branch target address (BT) Example beq $s,$s,lo next Branch taken if equal, else increment by 2:2 2:6 2 : RegWrite = Branch = RegDst = LUSrc = LUControl 2 2:6 : Zero LU MemWrite = MemToReg = Compute BT I I Pseudo-Direct ddressing (Revisited) The J and JL instructions are encoded using the J-type. But, the address is not bits, only 26 bits bits addr 26 bits -bit Pseudo-Direct ddress is computed as follows: Bits to (least significant) are always zero because word alignment of code. Bits 27 to 2 is taken directly from the addr field of the machine code instruction. Bits to 28 are obtained from the four most significant bits from. j instruction RegWrite Branch RegDst Jump LUSrc MemWrite LUControl MemToReg 2:2 Zero 2:6 2 2 :28 27: 2: : 2:6 : LU I I

8 Path for s H add,sub,and,or,slt,addi,lw,sw,beq,j 29 RegWrite Branch RegDst Jump LUSrc MemWrite LUControl MemToReg 2:2 Zero 2:6 2 2 :28 27: 2: : 2:6 : LU I cknowledgement: The structure and several of the good examples are derived from the book Digital Design and Computer rchitecture (2) by D. M. Harris and S. L. Harris. I I What to Control We should set the control RegWrite Branch RegDst Jump signals depending on the LUSrc MemWrite instruction. LUControl MemToReg 2:2 Zero 2:6 2 2 :28 27: 2: : 2:6 : LU I R-Type I-Type J-Type Control Unit Input: Machine Code 6 bits rd shamt 6 bits 6 bits For I-Type and J-Type, the control signals depend on the field 6 bits addr 26 bits funct 6 bits For the R-Type, the field is. The control signals depend on the funct field I

9 Control Unit Structure H LU Decoder The 6 bits field from all instruction types Internal signal LUOp LUOp = means add LUOp = means subtract LUOp = look at the funct field LUOp = n/a 6 LUOp Main Decoder 2 RegWrite RegDst LUSrc Branch MemWrite MemToReg Jump Control signals to the data path Enough to check one bit (faster decoding) funct LUOp funct LUControl (add) (subtract) (add) (add) 6 LUOp 2 LU Decoder LUControl The 6 bits funct field from the R-type. Ignored if other types. funct 6 LU Decoder LUControl (sub) (subtract) (and) (and) (or) (or) (slt) (set less than) I I Main Decoder H E Performance nalysis (/2) General View 6 How should we analyze the performance of a computer By clock frequency By instructions per program RegWrite RegDst LUSrc Branch MemWrite MemToReg Jump LUOp R-Type lw Execution time (in seconds) = # instructions clock cycles instruction seconds clock cycle sw beq addi umber of instructions in a program (# = number of) Determined by programmer or the compiler or both. verage cycles per instruction (CPI) Determined by the microarchitecture implementation. Seconds per cycle = clock period T C. Determined by the critical path in the logic. j Problem: Your program may have many inputs. ot only one specific program might be interesting. Solution: Use a benchmark (a set of programs). Example: SPEC CPU Benchmark I I

10 7 verage cycles per instruction (CPI) clock cycle Seconds per cycle = clock period TC. Determined by the microdetermined by the architecture implementation. critical path in the logic. Each instruction takes one clock cycle. That is, CPI =. I Zero MemToReg : : 2: 2 2:6 2 2:6 :28 27: LUControl 2:2 The main problem with this design is the long critical path. The lw instruction has longer path than R-Type instructions. However, because of synchronous logic, the clock period is determined by the slowest instruction. MemWrite LUSrc Determined by programmer or the compiler or both. instruction Branch RegWrite RegDst Jump 9 umber of instructions in a program (# = number of) seconds LU # instructions clock cycles Execution time = (in seconds) 8 Critical Path Example: Load Word (lw) Performance nalysis (2/2) I Reading Guidelines Summary Some key take away points: The LU performs most of the arithmetic and logic computations in the processor. Module (Processor Design) P&H Chap. (except.9,.,.2) P&H ppx. B (review) Exercise Main content in Chapter in the coue book. See also the tional book by Harris & Harris (see coue web page) You need to review logic design. See ppendix B and slides on the coue website. I The data path consists of sequential logic that performs processing of words in the processor. The control unit decodes instructions and tells the data path what to do. The single-cycle processor has a long critical path. We will solve this in the next lecture by introducing a pipelined processor. Thanks for listening! I