CSc 256 Midterm 2 Spring 2012

Transcription

1 CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble $12, 0x , there Translate this MIPS instruction to an efficient sequence of machine language instructions. You only have to show the text form of the machine language instructions; don't translate into binary. Leave the branch target as the label there; don t worry about calculating its address etc. ANS: lui $1, 0x2000 ori $1, $1, 0x4881 slt $1, $12, $1 bne $1, $0, there 1b) This is a memory location that contains a MIPS instruction: address [0x ] contents 0x00e28824 Translate it into the MIPS assembly language instruction (show the operation, operands, etc): (13 points) ANS: and $17, $7, $2

2 1c) You are given a MIPS branch instruction: x: beq $12, $0, y The address of the label "y" is 0x4006e4. The memory location at "x" contains: address contents?????? which represents the beq instruction. Find the address of the label x. (12 points) ANS: 0x400a0c [Work:] BTA = &branch offset Offset = x4006e4 = &x xfffffcd4 &x = 0x4006e4 0xffff fcd8 = 0x4006e4 + 0x328 = 0x400a0c

3 Problem 2: a) Consider this digital logic circuit: Fill out an equivalent truth table for the circuit. (12 points) X2 X1 X0 Y

4 b) Fill out a truth table for this digital logic circuit. (8 points) X1 X0 Y

5 Problem 3: Refer to the MIPS single-cycle datapath in the sheets provided. Show the control signals for the MIPS instructions, in the table below. Note that some of the control signals have new names. (30 points) Hint: ALUOp control bits are 00 (force ALU to add), 01 (force ALU to subtract), 10 (follow operation specified by bits 5-0 of instruction word) [SelA is ALUSrc, SelB is RegDst, SelC is branch, SelD is MemToReg] a) beq MemRead MemWrite SelA SelB SelC SelD ALUOp1 ALUOp0 RegWrite X 0 0 x 1 x b) lw MemRead MemWrite SelA SelB SelC SelD ALUOp1 ALUOp0 RegWrite

6 Problem 4: For the MIPS single-cycle datapath given, suppose we build a new implementation using different technology. These are the latencies through the main components: Register Read Register Write ALU operation Memory Read Memory Write T R ps T R ps 300 ps 600 ps 600 ps a) We are given that the time taken for an R-type instruction to complete (i.e., the latency of the R-type instruction) is 1200 ps. Solve for T R. (8 points) 1200 ps = T R T R 2 T R = 300 T R = 150 ps b) How much time does a lw take to complete? (6 points) lw latency = = 1800 ps

7 c) What is the clock rate in MHz for this new MIPS implementation? You don t have to give the actual number as the answer; just show an equation that can be solved to get the clock rate in MHz. (Hint: 1 ps = 10^-12 seconds, 1 ns = 10^-9 seconds, 1 MHz = 10^6 Hz.) (6 points) ANS: Clock rate = 1 / (1800 * 10^-12) Hz = 10^12 / 1800 Hz = 10^6 / 1800 MHz

8 MIPS instructions op1, op2 are registers, op3 is register or constant cont[op1] means contents of op1 move op1, op2 cont[op1] = cont[op2] add op1, op2, op3 cont[op1] = cont[op2] + cont[op3] sub op1, op2, op3 cont[op1] = cont[op2] - cont[op3] mul op1, op2, op3 cont[op1] = cont[op2] * cont[op3] div op1, op2, op3 cont[op1] = cont[op2] / cont[op3] rem op1, op2, op3 cont[op1] = cont[op2] % cont[op3] not op1, op2 cont[op1] = not cont[op2] (bitwise) and op1, op2, op3 cont[op1] = cont[op2] and cont[op3] (bitwise) or op1, op2, op3 cont[op1] = cont[op2] or cont[op3] (bitwise) nand op1, op2, op3 cont[op1] = cont[op2] nand cont[op3] (bitwise) nor op1, op2, op3 cont[op1] = cont[op2] nor cont[op3] (bitwise) xor op1, op2, op3 cont[op1] = cont[op2] xor cont[op3] (bitwise) sll op1, op2, AMT cont[op1] = cont[op2] shift left logical by AMT bits srl op1, op2, AMT cont[op1] = cont[op2] shift right logical by AMT bits sra op1, op2, AMT cont[op1] = cont[op2] shift right arithmetic by AMT bits rol op1, op2, AMT cont[op1] = cont[op2] rotate left by AMT bits ror op1, op2, AMT cont[op1] = cont[op2] rotate right by AMT bits b label j label beq op1, op2, label bne op1, op2, label bgt op1, op2, label bge op1, op2, label blt op1, op2, label ble op1, op2, label beqz op1, label bnez op1, label bgtz op1, label bgez op1, label bltz op1, label blez op1, label la R, label li R, constant lw R,?? goto label goto label if (cont[op1]==cont[op2]) goto label if (cont[op1]!=cont[op2]) goto label if (cont[op1]>cont[op2]) goto label if (cont[op1]>=cont[op2]) goto label if (cont[op1]<cont[op2]) goto label if (cont[op1]<=cont[op2]) goto label if (cont[op1]==0) goto label if (cont[op1]!=0) goto label if (cont[op1]>0) goto label if (cont[op1]>=0) goto label if (cont[op1]<0) goto label if (cont[op1]<=0) goto label cont[r] = address of label cont[r] = constant cont[r] = M[ADDR]

9 lb R,?? lbu R,?? sw R,?? sb R,?? cont[r] = m[addr], sign- extended cont[r] = m[addr], zero- extended M[ADDR] = cont[r] m[addr] = low 8- bits of cont[r] if?? is a label, ADDR = address of label if?? is (R), ADDR = cont[r] if?? is constant(r), ADDR = cont[r] + constant if?? is label(r), ADDR = cont[r] + address of label mtc0 op1, op2 contents of coprocessor 0 register op1 = contents of MIPS register op2 mfc0 op1, op2 contents of MIPS register op1 = contents of coprocessor 0 register op2 Syscall usage: print an int $v0=1, $a0=int to be printed print a string $v0=4, $a0=address of string to be printed read an int $v0=5, input int appears in $v0 exit $v0=10 MIPS register names: $0 $1 $2,$3 $v0,$v1 $4 - $7 $a0 - $a3 $8 - $15 $t0 - $t7 $16 - $23 $s0 - $s7 $24 - $25 $t8 - $t9 $26 - $27 $k0 - $k1 $28 $gp $29 $sp $30 $s8 $31 $ra

10 ss ssst tttt dddd d add rd,rs,rt ss ssst tttt dddd d sub rd,rs,rt ss ssst tttt mult rs,rt ss ssst tttt div rs,rt ss ssst tttt dddd d addu rd,rs,rt ss ssst tttt dddd d subu rd,rs,rt ss ssst tttt multu rs,rt ss ssst tttt divu rs,rt dddd d mfhi rd ss sss mthi rs dddd d mflo rd ss sss mtlo rs ss ssst tttt dddd d and rd,rs,rt ss ssst tttt dddd d nor rd,rs,rt ss ssst tttt dddd d or rd,rs,rt ss ssst tttt dddd d xor rd,rs,rt ss ssst tttt dddd d sllv rd,rt,rs ss ssst tttt dddd d srlv rd,rt,rs ss ssst tttt dddd d srav rd,rt,rs ss ssst tttt iiii iiii iiii iiii addi rt,rs,i ss ssst tttt iiii iiii iiii iiii addiu rt,rs,i ss ssst tttt iiii iiii iiii iiii andi rt,rs,i t tttt iiii iiii iiii iiii lui rt,i ss ssst tttt iiii iiii iiii iii ori rt,rs,i ss ssst tttt iiii iiii iiii iiii xori rt,rs,i t tttt dddd diii ii sll rd,rt,i t tttt dddd diii ii srl rd,rt,i t tttt dddd diii ii sra rd,rt,i bb bbbt tttt iiii iiii iiii iiii lw rt,i(rb) bb bbbt tttt iiii iiii iiii iiii lb rt,i(rb) bb bbbt tttt iiii iiii iiii iiii lbu rt,i(rb) bb bbbt tttt iiii iiii iiii iiii sw rt,i(rb) bb bbbt tttt iiii iiii iiii iiii sb rt,i(rb) ss sss iiii iiii iiii iiii bltz rs,i ss sss iiii iiii iiii iiii bgez rs,i ss sss iiii iiii iiii iiii blez rs,i ss sss iiii iiii iiii iiii bgtz rs,i ss ssst tttt iiii iiii iiii iiii beq rs,rt,i

11 ss ssst tttt iiii iiii iiii iiii bne rs,rt,i ss ssst tttt dddd d slt rd,rs,rt ss ssst tttt iiii iiii iiii iiii slti rt,rs,i ii iiii iiii iiii iiii iiii iiii j I ss sss jr rs ii iiii iiii iiii iiii iiii iiii jal I ss sss dddd d jalr rd,rs syscall