Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) Consulting hours. Milestone #1 (due 1/26)

Transcription

1 Lecture Topics Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) 1 Announcements Consulting hours Milestone #1 (due 1/26) Milestone #2 (due 2/2) 2 1

2 Review: Integer Operations Internal representation unsigned integers signed integers Operations arithmetic operations bitwise operations shift operations 3 Review: Operations on Integers Arithmetic operations: addition, subtraction multiplication, division Bitwise (logical) operations: AND, OR, XOR, Shift operations: SLL, SRL, SRA, 4 2

3 Bitwise Operations Almost all processors support: AND OR XOR Some processors support additional ops: NAND, NOR ANDN, ORN, XORN 5 Shift Operations Almost all processors support: SLL (shift left logical) SRL (shift right logical) SRA (shift right arithmetic) Some processors support additional ops: ROL (rotate left) ROR (rotate right) 6 3

4 Arithmetic Operations Almost all processors support: Addition Subtraction Most processors support additional ops: Multiplication Division 7 Combined Adder/Subtractor (4 bits) B3 B2 B1 B0 SUB A3 A2 A1 A0 A B A B A B A B Carry Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin S S S S S3 S2 S1 S0 SUB control signal: 0 means Add, 1 means Subtract 8 4

5 Multiplication Requires a series of steps (sequential circuit) First approach: based on paper and pencil assume 4 bit values assume positive values product is twice as long as operands multiplicand multiplier product Multiplication Algorithm Initialize 64-bit product to zero Repeat if bit 0 of multiplier is 1, add multiplicand to product shift multiplicand left 1 shift multiplier right

6 Multiplication Hardware Since product is 64 bits, use 64-bit adder and extend multiplicand to 64 bits with zeroes 11 Multiplication Hardware Extend with 0's Initialize to

7 Example (4-bit operands) 13 Improved Multiplication Initialize 64-bit product: zeroes in upper half, multiplier in lower half 14 7

8 Improved Multiplication No need for register to hold multiplier: place in lower 32 bits of product No need for double-length register to hold multiplicand 32-bit adder (instead of 64-bit adder) Shift product and multiplier at same time (equivalent to shifting multiplicand left) 15 Improved Multiplication Signed operands: work with 31-bit operands, "calculate" sign of product positive: sign bits the same negative: sign bits different Overflow: product must "fit" into lower 32 bits of 64-bit register; result is too large if upper 32 bits are not the same as the sign bit of the result (bit 31) 16 8

9 Faster Multiplier Unroll the loop: bit adders least significant bit of each sum is one bit in the product the other 31 bits and the carry out are the input to the next adder 17 Faster Multiplier Organize adders to minimize delay 18 9

10 Division Again, series of steps First approach: based on paper and pencil assume 4 bit values assume positive values dividend is larger than divisor quotient dividend divisor remainder Division Hardware Initially divisor in left half Initially dividend 20 10

11 Example (4 bit operands) 21 Improved Division One cycle per partial-remainder subtraction Same circuit as multiplication 22 11

12 Faster Divider Can t use parallel hardware as in multiplier, since subtraction is conditional on sign of remainder Faster dividers (such as SRT division) generate multiple quotient bits per step Uses a table to look up next guess Table must be accurate Still require multiple steps 23 MIPS Integer Circuits Math unit: addition and subtraction bitwise operations Shift unit: shift operations Multiply and Divide unit: multiplication and division 24 12

13 MIPS Math Unit Inputs: 32-bit operands 4-bit operation code Outputs: 32-bit result 1-bit zero flag 1-bit overflow flag 25 MIPS Math Unit Handles addition, subtraction and bitwise operations: ADD, ADDU SUB, SUBU AND, OR, XOR, NOR SLT, SLTU ADDU, SUBU do not set the overflow flag SLT, SLTU produce 0 or

14 MIPS Shift Unit Handles shift operations: SLL SRL SRA No provision for rotates (but can be done with a series of instructions) 27 MIPS Multiply Circuit Handles unsigned and signed multiply Circuit has two special registers to hold the result: HI and LO Product must be moved from LO to general purpose register 28 14

15 MIPS Multiply Circuit Unsigned multiplication: LO contains product HI contains zeroes (overflow otherwise) Signed multiplication: LO contains product Overflow if bit 31 (leftmost bit of LO) does not match all bits of HI 29 MIPS Divide Circuit Uses same circuitry as multiplication LO contains the quotient HI contains the remainder Circuit does not detect overflow or division by zero (must be handled by software) 30 15

16 MIPS ISA The MIPS was originally developed at Stanford (by Hennessy's group) Spun off to commercial company Typical RISC microprocessor small number of instructions only 32 general purpose registers 31 MIPS R-format Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction fields op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (00000 for now) funct: function code (extends opcode) 32 16

17 R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add = MIPS I-format Instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits Instruction fields rs: first source register number rt: destination or source register number Constant: 2 15 to Address: offset added to base address in rs Compromise: different formats complicate decoding, but allow uniform 32-bit instructions 34 17