Lecture 3: Instruction Set Architecture

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1 Lecture 3: Instruction Set Architecture

2 Interface Software/compiler instruction set hardware

3 Design Space of ISA Five Primary Dimensions Number of explicit operands ( 0, 1, 2, 3 ) Operand Storage Where besides memory? Effective Address How is memory location specified? Type & Size of Operands byte, int, float, vector,... How is it specified? Operations add, sub, mul,... Other Aspects How is it specifed? Successor How is it specified? Conditions How are they determined? Encodings Fixed or variable? Parallelism

4 Orthogonality ISA Metrics No special registers, few special cases, all operand modes available with any data type or instruction type Completeness Support for a wide range of operations and target applications Regularity No overloading for the meanings of instruction fields Streamlined Resource requirements can be easily determined Ease of compilation

5 Accumulator: Basic ISA Classes 1 address add A acc acc + mem[a] 1+x address addx A acc acc + mem[a + x] Stack: 0 address add tos tos + next General Purpose Register: 2 address add A B EA(A) EA(A) + EA(B) 3 address add A B C EA(A) EA(B) + EA(C) Load/Store: 3 address add Ra Rb Rc Ra Rb + Rc load Ra Rb Ra mem[rb] store Ra Rb mem[rb] Ra

6 Instruction set: +, -, *, /,... push A, pop A Stack Machines Example: a*b - (a+c*b) push a push b * push a push c push b * + - A B A A*B a A*B * A A*B - b a C A A*B + c * A A*B b A*B

7 Arguments Against Stacks Data does not always surface when needed Constants, repeated operands, common sub-expressions so TOP and SWAP instructions are required Code density is about equal to that of GPR instruction sets Registers have short addresses Keep things in registers and reuse them Slightly simpler to write a poor compiler, but not an optimizing compiler Performance derived from fast registers, not the way they are used.

8 A "Typical" RISC 32-bit fixed format instruction (3 formats) bit GPR (R0 contains zero, DP take pair) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement Simple branch conditions Delayed branch

9 Example: MIPS Register-Register Op Op Op Rs1 Register-Immediate Branch Op Rs2 Rs1 Rd immediate target Rd Opx Jump / Call shamt Rs1 Rs2/Opx immediate

10 Overview of MIPS simple instructions all 32 bits wide very structured only three instruction formats R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address

11 Instructions: bne $t4,$t5,label Next instruction is at Label if $t4 $t5 beq $t4,$t5,label Next instruction is at Label if $t4 = $t5 j Label Next instruction is at Label Formats: Addresses in Branches and Jumps I J op rs rt 16 bit address op 26 bit address

12 To summarize: MIPS operands Name Example Comments $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so 2 30 memory Memory[4],..., sequential words differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers, such as those saved on procedure calls. MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants load word lw $s1, 100($s2) $s1 = Memory[$s ]Word from memory to register store word sw $s1, 100($s2) Memory[$s ] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s ]Byte from memory to register store byte sb $s1, 100($s2) Memory[$s ] = $s1 Byte from register to memory load upper immediate lui $s1, 100 $s1 = 100 * 2 16 Loads constant in upper 16 bits branch on equal beq $s1, $s2, 25 if ( $s1 == $s2 ) go to PC branch on not equal bne $s1, $s2, 25 if ( $s1!= $s2 ) go to Conditional PC branch set on less than slt $s1, $s2, $s3 if ( $s2 < $s3 ) $s1 = 1; else $s1 = 0 Equal test; PC-relative branch Not equal test; PC-relative Compare less than; for beq, bne set less than immediate slti $s1, $s2, 100 if ( $s2 < 100 ) $s1 = 1; else $s1 = 0 Compare less than constant jump j 2500 go to Jump to target address Uncondi- jump register jr $ra go to $ra For switch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to For procedure call

13 Alternative Architectures Design alternative: provide more powerful operations goal is to reduce number of instructions executed danger is a slower cycle time and/or a higher CPI Sometimes referred to as RISC vs. CISC virtually all new instruction sets since 1982 have been RISC

14 Most Popular ISA of All Time: The Intel 80x : 8086 extension to 8080 (8 bit accumulator machine) 16 bit, additional registers 1980: 8087 floating point coprocessor adds 60 instructions hybrid stack/register scheme 1982: bit address space memory mapping and protection model

15 Most Popular ISA of All Time: The Intel 80x : bit address space 32-bit GP registers paging , Pentium, Pentium Pro 1997 MMX added

16 80x86 Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destination one operand can come from memory complex addressing modes e.g., base or scaled index with 8 or 32 bit displacement Saving grace: the most frequently used instructions are not too difficult to build compilers avoid the portions of the architecture that are slow

17 Intel 80x86 Integer Registers

18 Intel 80x86 Floating Point Registers

19 Usage of Intel 80x86 Floating Point Registers NASA 7 Spice Stack (2nd operand ST(1)) 0.3% 2.0% Register (2nd operand ST(i), i>1) 23.3% 8.3% Memory 76.3% 89.7% Above are dynamic instruction percentages (i.e., based on counts of executed instructions)

20 80x86 Addressing/Protection

21 80x86 Instruction Format 8086 in black; extensions in color (Base reg + 2 Scale x Index reg)

22 reg 80x86 Instruction Encoding: Mod, Reg, R/M Field r w=0 w=1 r/m mod=0 mod=1 mod=2 mod=3 16b 32b 16b 32b 16b 32b 16b 32b 0 AL AX EAX 0 addr=bx+si =EAX same same same same same 1 CL CX ECX 1 addr=bx+di =ECX addr addr addr addr as 2 DL DX EDX 2 addr=bp+si =EDX mod=0 mod=0 mod=0 mod=0 reg 3 BL BX EBX 3 addr=bp+si =EBX +d8 +d8 +d16 +d32 field 4 AH SP ESP 4 addr=si =(sib) SI+d8 (sib)+d8 SI+d8 (sib)+d32 5 CH BP EBP 5 addr=di =d32 DI+d8 EBP+d8 DI+d16 EBP+d32 6 DH SI ESI 6 addr=d16 =ESI BP+d8 ESI+d8 BP+d16 ESI+d32 7 BH DI EDI 7 addr=bx =EDI BX+d8 EDI+d8 BX+d16 EDI+d32 w from opcode r/m field depends on mod and machine mode First address specifier: Reg=3 bits, R/M=3 bits, Mod=2 bits

23 80x86 Instruction Encoding Sc/Index/Base field sib Index Base 0 EAX EAX 1 ECX ECX 2 EDX EDX 3 EBX EBX 4 no index ESP 5 EBP if mod=0, d32 if mod 0, EBP 6 ESI ESI 7 EDI EDI Base + Scaled Index Mode Used when: mod = 0,1,2 in 32-bit mode AND r/m = 4! 2-bit Scale Field 3-bit Index Field 3-bit Base Field

24 80x86 Addressing Mode Usage for 32-bit Mode Addressing Mode GccEspr.NASA7 Spice Avg. Register indirect 10% 10% 6% 2% 7% Base + 8-bit disp 46% 43% 32% 4% 31% Base + 32-bit disp 2% 0% 24% 10% 9% Indexed 1% 0% 1% 0% 1% Based indexed + 8b disp 0% 0% 4% 0% 1% Based indexed + 32b disp 0% 0% 0% 0% 0% Base + Scaled Indexed 12% 31% 9% 0% 13% Base + Scaled Index + 8b disp 2% 1% 2% 0% 1% Base + Scaled Index + 32b disp 6% 2% 2% 33% 11% 32-bit Direct 19% 12% 20% 51% 26%

25 Length in bytes % 0% 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 2% 2% 4% 3% 4% 6% 27% 13% 12% 13% 15% 12% 3% 4% 1% 3% 29% 27% 16% 21% 24% 24% 17% 23% 25% 24% 19% 24% 80x86 Length Distribution 0% 10% 20% 30% % instructions at each length Espresso Gcc Spice NASA7

26 Instruction Counts: 80x86 v. DLX SPEC pgm x86 DLX DLX 86 gcc 3,771,327,742 3,892,063, espresso 2,216,423,413 2,801,294, spice 15,257,026,309 16,965,928, nasa7 15,603,040,963 6,118,740,

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