Integer Arithmetic. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University

Transcription

1 Integer Arithmetic Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong

2 Where Are We? Abstraction Layers in Modern Systems Scope of this course Application Algorithm Programming Language Operating System/Virtual Machine Instruction Set Architecture (ISA) Microarchitecture Gates/Register-Transfer Level (RTL) Circuits Devices Physics SW (HW/SW Interface) Ch. 2 Ch. 3, 4 and 5 HW * Sources: CS 252 lecture notes from Prof. Kubiatowicz (UC Berkeley). Coursera lecture notes for HW/SW Interface from Profs. Borriello and Ceze (Univ. of Washington). EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 2

3 Introduction Bits are just bits No inherent meaning: conventions define relationship between bits and numbers n-bit binary numbers: 0 ~ 2 n -1 decimal numbers Of course it gets more complicated Numbers are finite (overflow) Negative numbers Fractions and real numbers Precision and accuracy Error propagation,... EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 3

4 Arithmetic for Computers: An Overview Operations on integers Textbook: P&H (for both 4 th and 5 th Editions) Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Textbook: P&H 3.5 Representation and operations EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 4

5 Integer Addition & Subtraction EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong

6 Integer Addition Example: Overflow if result out of range Adding +ve and ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two ve operands Overflow if result sign is 0 EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 6

7 Integer Subtraction Add negation of second operand Example: 7 6 = 7 + ( 6) +7: : : Overflow if result out of range Subtracting two +ve or two ve operands, no overflow Subtracting +ve from ve operand Overflow if result sign is 0 Subtracting ve from +ve operand Overflow if result sign is 1 EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 7

8 Simple Adder (n-bit ripple-carry adder) n-bit ripple-carry adder EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong 8

9 Dealing with Overflow Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong 9

10 Arithmetic for Multimedia Graphics and media processing Operates on vectors of 8-bit and 16-bit data Use 64-bit adder, with partitioned carry chain Operate on 8 8-bit, 4 16-bit, or 2 32-bit vectors SIMD (single-instruction, multiple-data) Saturating operations On overflow, result is largest representable value c.f. 2s-complement modulo arithmetic E.g., clipping in audio, saturation in video EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 10

11 Integer Multiplication EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong

12 Multiplication Start with long-multiplication approach multiplicand multiplier product Length of product is the sum of operand lengths EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong 12

13 Multiplication Hardware Initially 0 EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 13

14 Optimized Multiplier Perform steps in parallel: add/shift One cycle per partial-product addition That s ok, if frequency of multiplications is low EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 14

15 Faster Multiplier Uses multiple adders Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong 15

16 MIPS Multiplication Two 32-bit registers for product HI: most-significant 32 bits LO: least-significant 32-bits Instructions mult rs, rt / multu rs, rt 64-bit product in HI/LO mfhi rd / mflo rd Move from HI/LO to rd Can test HI value to see if product overflows 32 bits mul rd, rs, rt Least-significant 32 bits of product > rd EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 16

17 Integer Division EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong

18 Division divisor quotient dividend remainder n-bit operands yield n-bit quotient and remainder Check for 0 divisor Long division approach If divisor dividend bits 1 bit in quotient, subtract Otherwise 0 bit in quotient, bring down next dividend bit Restoring division Do the subtract, and if remainder goes < 0, add divisor back Signed division Divide using absolute values Adjust sign of quotient and remainder as required EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 18

19 Division Hardware Initially divisor i n left half Initially dividend EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 19

20 Optimized Divider One cycle per partial-remainder subtraction Looks a lot like a multiplier! Same hardware can be used for both EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 20

21 Faster Division Can t use parallel hardware as in multiplier Subtraction is conditional on sign of remainder Faster dividers (e.g. SRT devision) generate multiple quotient bits per step Still require multiple steps EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 21

22 MIPS Division Use HI/LO registers for result HI: 32-bit remainder LO: 32-bit quotient Instructions div rs, rt / divu rs, rt No overflow or divide-by-0 checking Software must perform checks if required Use mfhi, mflo to access result EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu) 22