The Stored Program Computer

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Susanna Parrish
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1 The Stored Program Computer : John von Neumann Wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC also Alan Turing Konrad Zuse Eckert & Mauchly The basic structure proposed in the draft became known as the von Neumann machine (or model). a memory, containing instructions and data a processing unit, for performing arithmetic and logical operations a control unit, for interpreting instructions

2 von Neumann Model 2 stores both program instructions and data implements a next state function Abstraction of von Neumann

3 Memory 3 2 k x m array of stored bits Address unique (k-bit) identifier of location Contents m-bit value stored in location Basic Operations LOAD read a value from a memory location STORE write a value to a memory location

4 Interface to Memory How does processing unit get data to/from memory? MAR: Memory Address Register MDR: Memory Data Register MEMORY 4 To LOAD a location (A): Write the address (A) into the MAR. Send a read signal to the memory. Read the data from MDR. MAR MDR To STORE a value (X) to a location (A): Write the data (X) to the MDR. Write the address (A) into the MAR. Send a write signal to the memory.

5 Hardware Level Organization 5 Major components: - memory - central processing unit - registers - the fetch/execute cycle CPU PC IR Ex Unit MAR MBR I/O AR I/O BR System Bus Main Memory 0 (the hardware process) I/O Module Data Data Data n-1 buffers PC IR MAR MBR I/O AR I/O BR = program counter = instruction register = memory address register = memory buffer register = I/O address register = I/O buffer register

6 Central Processing Unit Control - decodes instructions and manages CPU s internal resources 6 Registers - general-purpose registers available to user processes - special-purpose registers directly managed in fetch/execute cycle - other registers may be reserved for use of operating system - very fast and expensive (relative to memory) - hold all operands and results of arithmetic instructions (on RISC systems) - save bits in instruction representation Data path or arithmetic/logic unit (ALU) - operates on data

7 Stored Program Concept s are collections of bits Programs are stored in memory, to be read or written just like data 7 memory for data, programs, compilers, editors, etc. Main Memory 0 PC CPU MAR IR MBR Ex Unit I/O AR I/O BR Data Data Data n-1 Fetch & Execute Cycle s are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the next instruction and continue

8 Stored Program Concept 8 Of course, on most systems several programs will be stored in memory at any given time. On most contemporary systems instructions of only one of those will be executed at any given instant. Main Memory PowerPoint pgm (machine code) vim (machine code) GIS source code (data) CPU PC IR Ex Unit MAR MBR I/O AR I/O BR g++ (machine code) The operating system will rapidly switch among the eligible processes, producing the illusion that several programs are executing at the same time.

9 Fetch/Execute Cycle Sometimes called the hardware process executes continuously. 9 Fetch Stage Execute Stage START Fetch Next Execute HALT Steps: - fetch an instruction from memory to the instruction register - increment the program counter register (by the instruction length) - decode the instruction (in the control unit) - fetch operands, if any, usually from registers - perform the operation (in the data path); this may modify the PC register - store the results, usually to registers

10 Simplified MIPS Datapath 10 ALU Memory Register File Memory

11 Finite State Machine So, where's the FSM? 11 Next Input Execute Input devices Current State Output devices Contents of registers and memory

12 Control Unit State Diagram Here's a state machine diagram for the MIPS control logic we'll be studying: 12

Hardware Level Organization

Hardware Level Organization Intro MIPS 1 Major components: - memory - central processing unit - registers - the fetch/execute cycle CPU PC IR Ex Unit MAR MBR I/O AR I/O BR System Bus Main Memory 0 (the