1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z

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1 CS W S Solutions for Midterm Exam 3/3/05. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z (8 pts) Generate a POS (product of sums) expression for (Show your work.) Easiest solution is via use of adding out (dual of multiplying out). In this case there are two steps. Note use of simplifying identity en route. Also note that if the goal is a POS expression, multiplying out is a step in the wrong direction--several students did this at the start. Considering X as A, Y as A less efficient solution is to generate the dual expression, multiply it out,to get a SOP expression, and then find the dual of the result, which will be the desired POS expression. This replaces one use of adding out with one use of multiplying out and two operations consisting of finding duals of expressions. The only advantage is that most of us have more skill in multiplying out than in adding out. 3. Find a simple expression describing the function generated by a given circuit, which is an XOR network in tree form. Some inputs consist of complemented variables and the components are XOR-gates and inverters. This is a very easy problem that can be solved by inspection if one understands the XOR operation. Looking at the circuit we see two inverters and observe that two of the input variables are complemented. Complementing operations cancel out in pairs, so that if, as in this case, there are an even number of them, we can ignore them all. So the given circuit simply adds, modulo 2, all the inputs. Since, those inputs that appear twice (A and B in this case) cancel out and so simply disappear, leaving the result for the give problem, (choice c.)

2 4. Find an expression for the function realized by the given NAND-gate circuit. E A Z C B V D The simplest way to deal with such problems is to convert the gates to AND- or ORgates. Starting from the right end of the given circuit, by considering it as a 2-stage AND-gate circuit, equivalent, as we saw in class--and in the text-- to a 2-stage AND-OR circuit, we can easily see that Z = E+AV (where V is the output of the left part of the circuit). Note the use of E rather than. Think of the inverter as a -input NAND-gate. Now we need to find V. It is the output of another 2-stage NAND-gate circuit. It is easy to see that V=. Putting together these two parts we have Z=E+A( ),which is choice e. 5. Using Boolean algebra identities, simplify Z =. The consensus of the first and third terms, Adding this to the expression allows us to use the absorption theorem to eliminate ACDF. Then we use the consensus theorem in the other direction to get rid of ACD, leaving the simplified expression Z = This is choice b. 6. Find an expression for the function realized by a MUX controlled by the NOR of and D, with -input A and 0-input B. Abbreviating the control input as K, the function is KA+ B. K is the complement of +D. So we have Z=C A+( +D)B=AC +BD. 7. (a) Write the dual of the expression Swap AND and OR operations. This yields Z D =((A+ careful to use parens to indicate the operands correctly. +F). You have to be (b) Write the complement of the above expression. The complement of any expression can easily be found from the dual by simply complementing all literals. So, from the above answer to part a, we can immediately write the complement as

3 8. 3. (0 pts) Suppose we are trying to find a minimal SOP expression for the function mapped below. For our first step, we would like to choose a subcube that is guaranteed (without our looking ahead) to be included in a minimal covering. Specify all the subcubes meeting this requirement, along with the point in the map that justifies this choice. State your answers in the form typified by 000,. Do not go any further with the problem. A ANSWERS D B - C POINT SUBCUBE 000 BD 00 BD 00 CD 0 ABD Examine each -point. For each, ask what cubes corresponding to prime implicants (pi s) cover it. These cubes are maximal, in the sense that none of them are wholly contained in a larger cube. Look at It is covered by and also by. Neither dominates the other in that they cost the same and each contains at least one -point not contained in other. So 0000 does NOT dictate a choice of a pi. Similar arguments can be made about 000, 00, 000. On the other hand, 000 is uniquely covered by, as is 00. The point 00 is covered by, and by no other pi. The point 0 is more interesting in that it is covered by and by BCD. But covers all -points covered by BCD and does not cost more. So we can say that it dominates all cubes covering 0, and therefore its inclusion in an optimum solutions is dictated by 0. Note that, if we knew nothing else, we could not be sure that there was no other equally costly solution that used BCD rather than to cover 0, but we CAN be sure that there is at least one optimal solution containing Each of the other -points is covered by more than pi. For example, 000 is covered by So the answer is: (000,, (00,, (00, 0,

4 9. Below is a partial diagram of an OR-to-AND type PLA (these are implemented with NOR-gates). Add as many additional vertical lines as you need and then program the PLA to realize, efficiently, the three functions, Z =(A+B, Z 2 =(A B), Z 3 =A B. A B We are dealing here with a circuit form that corresponds to POS expressions. So we should express Z3= in its POS form, which is (A+B)( ). Now we can see that A and Z3 can share the (A+B) term. So we will need a total of 3 columns, each corresponding to a first level NOR-gate (which corresponds to a first level AND-gate in an AND-OR circuit.) The above solution is valid, with the columns from left to right generating (A+B), ), and ( ). 0. We need a synchronous sequential circuit that will output a for every 0-input that terminates a block of at least 2 consecutive s. This is illustrated by the sample sequence below: X: Z: X 0 Z Z2 Z3 * 2 3,0,0, 2,0 3,0 3,0 Row- of the table represents, not only the starting state, but also the state reached after any 0 in the input sequence. Row-2 is the state reached after the first in a -block has arrived, i.e., the very first of the sequence, OR the first after a 0. Row-3 is the state in which the last input is a that is preceded by at least one, i.e, state-3 corresponds to the interior of a -block of length at least equal to 2. So, when a 0 occurs with the system in state-3, this terminates a -block of length at least equal to 2 and hence the output is a. Note that the next-state is, since we must now wait for a new -block to begin.

5 . Find a minimal-row flow table equivalent to the flow table shown below. AB ,0 2,0 5, 4, 2 5,0, 3, 2,0 3 5,0 2,0 2, 4, 4 2,0 5,0 3, 4, 5 2,0 3,, 2,0 XX 25 2 XX XX XX XX 4 XX 3 XX XX 5 First construct the pair chart. Put X s in the entries for 2, 5, 23, 24, 35, and 45 to indicate that rows with different output patterns are distinguishable. Then, for the other cells in the pair chart indicate the immediate implications. For example in the 4-position put entries 24 and 35 to indicate that 4 implies 24 and 35. Next, for each position with an X, put an X in every cell with a pointer to that position. For example, due to the X in 35, we put an X in 4 because 4 has a 35 entry. After completing this operation for a particular cell with an X, add a second X to that cell to indicate that we are finished with it. Continue until there are no single X s remaining, which is the situation shown in above diagram. Starting at the left end, we then find the equivalence classes for each column in turn by adding to the column designator all rows of that column that do not have X s in that column. If state i has already been put in an equivalence class, we do not consider column-i. In the present case, we find the equivalence classes to be simply 3 and 25. We must also add the degenerate -member class 4, since we need to account for all states of the original table. So the equivalence classes are {3, 25,4}. We now construct a reduced table with -row for each equivalence class. This is shown below. We assign a row of the new table to each of the equivalence classes. For example, assigning row to the class 3, we make the output pattern for row- the same as that for the members of the 3 class, namely 00. The next state entry for the 00 column of row- must correspond to a state equivalent to the next-state entries of both and 3 of the original table in the 00-column. These are 2 and 5, the set assigned to row-2 of the reduced table. So we make the next-state entry in column-00 of row- of the new table a 2. AB (3) 2,0 2,0 2, 3, (25) 2 2,0,, 2,0 (4) 3 2,0 2,0, 3, 2. For the flow matrix shown below, using the given state assignment, generate minimal SOP expressions for Y, Y2, and Z. Do not go any further with the design. AB y y2 2,0 3,0-3, ,0 2,0-3, 0 3,0 2,0 -,0 Consider Z first. The only -entries are in rows and 2 of column-0. We can uniquely characterize rows- and 2 by specifying y=0. Since the -column has only don t cares, we can specify the input for X= as simply A (this includes A and AB,which is OK due to the don t cares.). So the term is a minimal specification for Z. The y-variable is only for row-3. Therefore, for every state where the next-state is 3, we want Y to be. The above term ( ) for Z captures two of the 3 s in flow table-- without including any next-state entries other than 3. The remaining 3 (in the 0-column

6 of row-) is in the row uniquely characterized by y2=0. Again exploiting the don t care column, we could use B to specify the input. So the term B 2 specifies this entry correctly. Thus the expression B 2 is the most efficient SOP expression for Y. The state-variable y2 is for both rows 2 and 3. So Y2 should be set to for every state where the next state entry is 2 or 3. Every next-state entry in columns 0 and, specified by B=, is either a 2, a 3, or a don t care. The same is true for rows and 2, which are characterized by y=0. So the expression B+ captures every state where the next-state entry is 2 or 3, and NO state where it is specified at. So a valid and economical expression for Y2 is Y2= B+ The same results could be obtained more formally by generating a K-map for Z directly from the flow table (taking care to make the bottom row corresponding to the unused 0-state of yy2 all don t cares), and generating K-maps for Y and Y2 from the Y- matrix, which is easily derived from the flow table by making all next-state entries that are, 2, and 3 respectively, 00, 0, and. Again, don t cares are placed in column and in row 0.

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