Programmable Logic Design Grzegorz Budzyń Lecture. 15: Advanced hardware in FPGA structures

Transcription

1 Programmable Logic Design Grzegorz Budzyń Lecture 15: Advanced hardware in FPGA structures

2 Plan Introduction PowerPC block RocketIO

3 Introduction

4 Introduction The larger the logical chip, the more additional hardware coprocessors are available Themost popular andusefulare: PCI Express ( PCIe) Endpoint/RootPort blocks Very High-speed Serial communication blocks Hardware microcontrollers Ethernet Media Access Controller blocks DSP blocks Additional RAM and clock management blocks

5 PowerPC block

6 PowerPC Key Features Not availableinthenewestchips 1, MHz processor; achieve 2,200 DMIPS using a single FPGA with two processors New 5 x 2, 128-bit crossbar switch minimizes latency and enables point-to-point connectivity Simultaneous memory bus and Processor Local Bus (PLB) access maximizes throughput Integrated DMA channels, PLB interfaces, and dedicated memory interface minimize logic utilization

7 PowerPC Block Diagram Source: [1]

8 PowerPC Key Features Auxiliary Processor Unit (APU) controller to integrate hardware accelerators and create custom co-processors Non-blocking pipelined point-to-point access to TEMAC, PCIeblocks, and FPGA logic Dedicated memory interface port for up to 128-bit data transfer per cycle to offload PLB Highly pipelined transmit and receive scattergather DMA channels to maximize data transfer rates

9 PowerPC Key Features User selectable port prioritization and operating frequenciesto optimizesystem performance CPU-intensiveoperationssuchas video and3d data processing, andfloating-pointmathcanbe offloaded Optimized hardware/software partitioning maximizes FPGA utilization and minimizes hardware cost Double/single-precision arithmetic operations using IEEE 754-compatible FPU option

10 PowerPC Design Example Source: [1]

11 PowerPC core Features A fixed-point execution unit compliant with 32-bit architecture, containing thirty-two 32-bit general purpose registers (GPRs). PowerPC embedded-environment architecture extensions providing additionalsupport for embedded-systems applications: Flexible memory management Multiply-accumulate instructions for computationally intensive applications 64-bit time base 3 timers: programmable interval timer (PIT), fixed interval

12 PowerPC core Features Performance-enhancing features, including: Static branch prediction Five-stage pipeline with single-cycle execution of most instructions, including loads and stores Multiply-accumulate instructions Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide) Enhanced string and multiple-word handling Support for unaligned loads and unaligned stores to cache arrays, main memory,and on-chip memory (OCM) Minimized interrupt latency

13 PowerPC core Features Integrated instruction-cache: 16 KB, 2-way set associative Eight words (32 bytes) per cacheline Fetch line buffer Non-blocking during fetch line fills Integrated data-cache: 16 KB, 2-way set associative Eight words (32 bytes) per cacheline Read and write line buffers Programmable load and store cacheline allocation Operand forwarding during cacheline fills Non-blocking during cacheline fills and flushes

14 PowerPC core Features Flexible memory management: Translation of the 4 GB logical-address space into the physical-address space Independent control over instruction translation and protection, and data translation and protection Page-level access control using the translation mechanism Software control over the page-replacement strategy Write-through, cacheability, user-defined 0, guarded, and endian storage-attribute control for each virtualmemory region Additional protection control using zones

15 PowerPC core Organization Source: [1]

16 PCIe block

17 PCIe What s that In Xilinx devices there are available different versions of PCIe blocks in different devices The PCI Express block in Virtex-6FPGAs implements transaction layer, data link layer, and physical layer functions to provide complete PCI Express endpoint and root-port functionality with minimal FPGA logic utilization.

18 PCIe What s that

19 PCIe Key Features PCI SIG-verified Gen1 and Gen2 compliance Works with GTX transceivers to deliver PCIe endpoint and root port function Built-in hard IP frees user logic resources and reduces power Multiple PCIeblocks for increased bandwidth, multiple functions, or simultaneous implementation of endpoint and root port support in a single FPGA Scaleablebandwidth (x1, x2, x4, x8 at Gen1 and Gen2 data rates)

20 PCIe Key Features 8b/10b encode and decode Standardized user interface Easy-to-use packet-based protocol Full-duplex communication Back-to-back transactions enable greater link bandwidth utilization Supports flow control of data and discontinuation of an in-process transaction in transmit direction Supports flow control of data in receive direction Supports a maximum transaction payload of up to 1024 bytes

21 PCIe Block Diagram (Virtex) Source: [2]

22 PCIe Block Diagram (Spartan) Source: [2]

23 PCIe Applications Data communications networks Telecommunications networks Broadband wired and wireless applications Cross-connects Network interface cards Chip-to-chip and backplane interconnect Crossbar switches Wireless base stations

24 Ethernet MAC block

25 Ethernet MAC Features Fully integrated 10/100/1000 Mb/s Ethernet MAC Configurable full-duplex operation in 10/100/1000 Mb/s Configurable half-duplex operation in 10/100 Mb/s Media Independent Interface (MII) and Gigabit Media Independent Interface (GMII) when operating at 2.5V only, and Reduced Gigabit Media Independent Interface (RGMII)

26 Ethernet MAC Features 1000BASE-X Physical Coding Sublayer(PCS) and a Physical Medium Attachment(PMA) sublayerincluded for use with the Virtex-6 serial transceivers to provide a complete onchip 1000BASE-X implementation Support for 1000BASE-X overclockingup to 2500 Mb/s Serial Gigabit Media Independent Interface (SGMII) supported through the serial transceivers interfaces to external copper PHY layer for full-duplex operation

27 Ethernet MAC Features Management Data Input/Output (MDIO) interface to manage objects in the physical layer User-accessible raw statistic vector outputs Support for VLAN frames Configurable interframegap (IFG) adjustment in full-duplex operation Configurable support for jumbo frames of any length

28 Ethernet MAC Block diagram Source: [3]

29 Ethernet MAC Functional diagram Source: [3]

30 Ethernet MAC Interfaces

31 Ethernet MAC Primitive Source: [3]

32 Thank you for your attention

33 References [1] PowerPC Processor Reference Guide ; [2] LogiCOREIP Virtex-6 FPGA IntegratedBlockv1.5 for PCI Express ; [3] Virtex-6 FPGA EmbeddedTri-ModeEthernet MAC ;