Area Efficient Self Timed Adders For Low Power Applications in VLSI
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1 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) Area Effcent Self Tmed Adders For Low Power Applcatons n VLSI S.Bharath, M.SunandhaPreeth Assstant Professor, Dept. of ECE, Adhparasakth Engneerng College, Melmaruvathur,TamlNadu, Inda PG Student [VLSI desgn], Department. of ECE, Adhparasakth Engneerng College, Melmaruvathur, TamlNadu. Inda ABSTRACT: In today s world there s a great need for low power desgn and area effcent hgh performance n DIP (Dgtal Image Processng) systemin ths paper the proposed method presents a parallel sngle-ral self-tmed adder. It uses recursve method for performng mult bt bnary addton. Ths desgn attans good performance wthout any specal speedup crcutry. A practcal mplementaton s provded along wth a completon detecton unt. The mplementaton s regular and does not have any practcal lmtatons of hgh fan outs. The recursve method based adder consumes least power among other Self-tmed adders. In our work ths can be reduced wth proposed adder. Ths technque presents a pre-processng and post processng adder to mnmze the multpler technque. A hgh fan-n gate s requred though but ths s unavodable for asynchronous logc and s managed by connectng the transstors n parallel. Smulatons have been performed usng cadence tool and superorty of the proposed approach over exstng asynchronous adders. In ths proposed system we are usng a parallel prefx adder t s used to reduce the power consumpton, area effcently.smulaton of ths technque s carred out by the cadence tool CADENCE GPDK 180nm Technology KEYWORDS: Asynchronous crcuts, bnary adder. CMOS desgn dgtal arthmetc, multpler technque. I. INTRODUCTION Low power has emerged as a prncpal theme n today s electroncs ndustry. The need for low power has caused a major paradgm shft where power dsspaton has become as mportant a consderaton as performance and area. So ths Bnary addton s the sngle most mportant operaton that a processor performs. Polonky et al. (1999) proposed an self-tmed adder based on DI RSFQ prmtves Self-tmed or asynchronous desgn solves these problems by removng a global clockmost of the adders have been desgned for synchronous crcuts even though there s a strong nterest n clockless/asynchronous processors/crcuts..asynchronous crcuts do not assume any quantzaton of tme. Therefore, they hold great potental for logc desgn as they are free from several problems of clocked (synchronous) crcuts. Anset et al. (2002) presented an theory based on PMOS devces need to be szed up to attan the gate s performancein prncple, logc flow n asynchronous crcuts s controlled by a request-acknowledgment handshakng protocol to establsh a ppelne n the absence of clocks. Explct handshakng blocks for small elements, such as bt adders, are expensve. Cornelus et al. (2006) presented a new technque these dynamc crcuts are often favoured n hgh performance desgns because of the speed advantage offered over statc CMOS logc crcuttherefore, t s mplctly and effcently managed usng dual-ral carry propagaton n adders. In ths prncple, logc flow n asynchronous crcuts s manly controlled by a request-acknowledgment handshakng protocol to establsh a ppelne n the absence of clocks. Explct handshakng blocks for small elements, such as bt adders, are expensve. Choudary et al. (2010) presented a technque based on whch they proposed an addton operaton snce n ALU all other arthmetc operatons can be derved nterms of addton operatononlytherefore, t s mplctly and effcently managed usng dual-ral carry propagaton n adders.self-tmed refers to logc crcuts that depend on and/or engneer tmng assumptons for the correct operaton. Self-tmed adders have the potental to run faster averaged for dynamc data, as early completon sensng can avod the need for the worst case bundled delay mechansm of synchronous crcuts. Copyrght to IJIRSET DOI: /IJIRSET
2 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) PIPELINED ADDERS USING SINGLE RAIL ENCODING The asynchronou Req/Ack handshake can be used to enable the adder block as well as to establsh the flow of carry sgnalsthese dual-ral sgnals can represent more than two logc values (nvald, 0, 1) and therefore can be used to generate bt-level acknowledgment when a bt operaton s completed. DELAY INSENSITIVE ADDERS USING DUAL RAILENCODING Delay nsenstve (DI) adders are asynchronous adders that assert bundlng constrants or DI operatonsthere are many varants of DI adders, such as DI rpple carry adder (DIRCA) and DI carry look-ahead adder (DICLA). DI adders use dual-ral encodng and are assumed to ncrease complexty GENERAL BLOCK DIAGRAM OF PASTA The general archtecture of the adder s shown n Fg. 1. Theselecton nput for two-nput multplexers corresponds to the Req handshake sgnal and wll be a sngle 0 to 1 transton denoted by SEL. It wll ntally select the actual operands durng SEL = 0 and wll swtch to feedback/carry paths for subsequent teratons usng SEL = 1. The feedback path from the HAs enables the multple teratons to contnue untl the completon when all carry sgnals wll assume zero values.c. II. RECURSIVE FORMULA FOR BINARY ADDITION Let S j and C j +1 denote the sum and carry, respectvely, for th bt at the j th teraton. The ntal condton ( j = 0) for addton s formulated as follows S0= a b (1.1) C0+1 = a b (1.2) The j th teraton for the recursve addton s formulated by S j = S j 1 C j 1 0 < n (1.3) C j+1= S j 1 C j 1 0 n (1.4) The recurson s termnated at kth teraton when the followng condton s met: Ck n + Ck n 1+ +Ck = 0, 0 k n III. PROPOSED ADDER The addton of two bnary numbers can be formulated as a prefx problem a new technque for hgh speed n speculatve completon The correspondng parallel-prefx algorthms can be used for speedng up bnary addton and for llustratng and understandng varous addton prncples. Ths secton ntroduces a mathematcal and vsual formalsm for prefx problems and algorthms. Two categores of prefx algorthms can be dstngushed; the seral prefx, and the treeprefx Problems. Copyrght to IJIRSET DOI: /IJIRSET
3 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) In a prefx problem, n outputs (yn-1, yn-2,., y0) are computed from nnputs (xn-1, xn-2,.,x0) usng an arbtrary assocatve operator as follows (1.5) (1.6) The problem can also be formulated recursvely (1.7) (1.8) (1.9) Tree-prefx algorthms nclude parallelsm for calculaton speed-up, and therefore form the category of parallel-prefx algorthms. It represents a seral algorthm for solvng the prefx problemin the prefx tree, there are n columns, correspondng to the number of nput bts. The gates performng the operaton and whch work n parallel are arranged n the same row, and smlarly, the same gates connected n seres are placed n consecutve rows. Thus, the number of rows m corresponds to the number of bnary operatons to be evaluated n seres. The sum bts, s are fnally obtaned from a post processng step. Fg 1.2 Block Dagram of Parallel Prefx Adder Fg 1.3 Logc and symbols for Pre processng summaton Gates Copyrght to IJIRSET DOI: /IJIRSET
4 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) G A B K A B A B P A B (1.10) (1.11) (1.12) In the above equaton,. operator s appled on two pars of bts and, these bts represent generate and propagate sgnals used n addton. The output of the operator s a new par of bts whch s agan combned usng a dot operator or sem-dot operator wth another pars of bts. Ths procedural use of dot operator and sem-dot operator creates a prefx tree network whch ultmately ends n the generaton of all carry sgnals.in the fnal step, the sum bts of the adder are generated wth the propagate sgnals of the operand bts and the precedng stage carry bt usng a xor gate. Choudary(2008) proposed a new technque for basc arthmetc operaton for hgher automaton The sem-dot operator wll be present as last computaton node n each column of the prefx graph structures, where t s essental to compute only generate term, whose value s the carry generated from that bt to the succeedng teratons IV. MAC The Multply-Accumulate Unt (MAC) s the man computatonal kernel n DIP archtectures. The MAC unt determnes the power and the speed of the overall system; t always les n the crtcal path. Developng hgh speed and low power MAC s crucal to use DSP n the future WSN. In ths work, a fast and low power MAC Unt s proposed for 2D-DCT computaton. Multplcaton nvolves the generaton of partal products, one for each dgt n the multpler, These partal products are then summed to produce the fnal product The Multply-Accumulate Unt (MAC) s the man computatonal kernel n DIP archtectures. The MAC unt determnes the power and the speed of the overall system; t always les n the crtcal path. Developng hgh speed and low power MAC s crucal to use DSP n the future WSN. In ths work, a fast and low power MAC Unt s proposed for 2D-DCT computaton. Multplcaton nvolves the generaton of partal products, one for each dgt n the multpler, These partal products are then summed to produce the fnal product. Fg 1.4 Block dagram of Proposed MAC V. MUTIPLICATION THROUGH ADDERS Let the product regster sze be 16 bts. Let the multplcand regsters sze be 8 bts. Store the multpler n the least sgnfcant half of the product regster. Clear the most sgnfcant half of the product regster. Repeat the followng steps for 8 tmes: If the least sgnfcant bt of the product regster s "1" then add the multplcand to the most sgnfcant half of the product regster. Shft the content of the product regster one bt to the rght (gnore the shfted-out bt.) Shft-n the carry bt nto the most sgnfcant bt of the product regster Copyrght to IJIRSET DOI: /IJIRSET
5 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) Multpler s the man computatonal kernel n DIP archtectures. The Multpler unt determnes the power and the speed of the overall system. In ths work, proposed adder based on fast and low complexty Multpler Unt s proposed.in all DSP and mage processng applcaton Multpler wll be the basc unt. The overall performance s fully depends on Adder unt effcency. Multplcaton nvolves the generaton of partal products, one for each dgt n the multpler, These partal products are then summed to produce the fnal produced. VI. SIMULATIONS RESULTS Smulatons resultssmulaton output s to be obtaned by usng CADENCE n dgtal desgn envronment.the adder was desgned usng multplcaton technque.in ths method usage the area,power consumpton and tme are obtaned Fg 1.5Smulaton for Parallel Prefx Adder Fgure 4.1 shows the smulaton results of parallel prefx adder. It represents 8 bt hexadecmal values henceclock s not assgned. The tmng s vared for smulaton the carry and propagate values are descrbed for each nput and output values are assgned usng the force operaton the run tme s vared for each smulaton. Fg 1.6 Smulatons For Multpler output Copyrght to IJIRSET DOI: /IJIRSET
6 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) Fgure 4.10 shows the above result s thesmulaton waveform for multpler technque usng proposed adder. The clock and enable operatons are performed the clock value s 0 and enable operaton s 1the 4 bt are assgned multpler technque the values are dsplayed n hexadecmal values the pasta pns act as a a callng functon for each operaton and run tme for each bt s dscussed the reset opton s 0 the sum and carry operaton performs 8 bt representaton the sel act as a selecton operaton for nput the product s multpled usng adder the each bt shfts to the prevous for shft operaton and hence multpler s acheved Fg 1.7 Area for proposed adder Fgure 1.7 shows the area wndow for proposed adder and hence area s 1537 for proposed method and hence compared wth the exstng system the cells are assgned wth 64 cells the delay tmng s less acheved for proposed system the tmng analyss s acheve for hgh performance the 16 bt values are assgned wth hexadecmal and callng functon s separately assgned for each module the area s reduced when compared wth the exstng system usng pasta module Copyrght to IJIRSET DOI: /IJIRSET
7 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) Fg1.8 RTL Vew of Multpler Output Fgure 1.8 shows the RTL vew of multpler output assgned wth pasta blocksn the crcut the block are assgned separately for each module and pasta pns act as a callng functon for each values n the multpler technque the separate module act as a callng functon for each block fnally the product s assgned wth each bt n the multpler technque usng multplcaton through addton process the mux act as a callng functon n the crcut16 bt s assgned for multpler technque VII. CONCLUSION A parallel prefx adder desgn s proposed for overall power consumpton. The proposed adder provdes overall area and power than the prevous methods. The parallel asynchronous self tmed adder crcut s effcently descrbed usng a handshakng protocol and also compared wth other adders proposed adders. The MAC unt s mplemented and the process s acheved effcently. Smulaton results demonstrate the effectveness of the proposed framework n parallel prefx adder usng multplcaton through addton process. The proposed method s mplemented usng dgtal CADANCE envronment REFERENCES [1] Brent. R.P, and Kung H.T, Aregular layout for parallel adders,ieeetransacton on Computer, vol. 49 C-33,volpp [2] Cheng F.-C, Unger. S. H, and Theobald. M, Self tmed carry- look ahead Adders, IEEE Transactons on Computer, vol. 49, no. 7, pp (2002) [3] Choudhury.P, Sahoo.S and Chakroborty. MImplementaton of basc arthmetc operatons usng cellular automaton, Proceedngs ofinternatonal centre for Informaton Technology, pp (2008) [4] Cornelus. C, Koppe.S, and Tmmermann. D Dynamc crcut technques n deep submcron technologes: Domno logc reconsdered, n Proceedngs of IEEEInternatonal conference on Integrated crcuts desgn Technology, vol. 6, pp. 1 4.(2006) [5] Geer.D, Is t tme for clock less chps? Asynchronous processor chps, IEEE Computer., vol. 38, no. 3, pp (2005) [6] Govndarajulu. S, Jayachandra Prasad. T, Consderatons of Performance Factors n CMOS Desgns, Internatonal conference on educatonal development, vol. 6, no. 4, pp (2008). [7] Kursun. V and Fredman.E.G, Domno logc wth dynamc body Based keeper, n Proceedngs of Sold- State Crcuts Conference. pp (2002) [8] Lu. W, Gray. C.T, Fan. D, and Far low. W.J, A 250-MHz wave ppelned adder n 2-μm CMOS, IEEEJournals on Sold-State Crcuts, vol. 29, no. 9, pp (1994) Copyrght to IJIRSET DOI: /IJIRSET
8 ISSN(Onlne): ISSN (Prnt) : Internatonal Journal of Innovatve Research n Scence, Engneerng and Technology (An ISO 3297: 2007 Certfed Organzaton) [9] Lo. J.C, A Fast Bnary Adder wth Condtonal Carry Generaton, IEEE Transactons on Computers, vol. 46, No. 2, pp (1997) [10] Lynch. T, Swartz lander Jr E.E.A Spannng Tree Carry Look ahead Adder, IEEE Transactons on Computers, vol. 41, No. 8, pp (1992) [11] Martn. A.J Asynchronous data paths and the desgn of asynchronous adder, Form. Methods vol. 19, no.4 pp (1992) [12] Maezawa. M and Polonsky.S, Dual-ral RSFQ shft regster on delay-nsenstve model and ts applcatons, Technology Representaton of Insttute of electroncs Informaton and Communcaton Engneerng, vol. 9, 97-29, pp (1997) [13] Nowck. S, Desgn of a low-latency asynchronous adder usng speculatve completon, IEEE Proceedngs of Computer Dgtal Technology, vol. 143, no. 5, pp (1996) [14] Rahman M.Z and Klee man. L (2013), A delay matched approach for the desgn of asynchronous sequental crcuts, Department of Computer System Technology Internatonal Journal on Computer vol.29, no. 6, pp (2013) [15] Von Neumann.J (1966) The Theory of Self-Reproducng Automata, IEEE Transacton on crcuts and system, vol. 55 no. 8, pp (1966) Copyrght to IJIRSET DOI: /IJIRSET
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