FIFO Service with Differentiated Queueing

Transcription

1 ANCS /29 FIFO Service with Differentiated Queueing Martin Karsten David R. Cheriton School of Computer Science University of Waterloo (currently on Sabbatical at University of Kaiserslautern) ANCS 2011

2 Motivation residential access link concurrent flows: file transfer (using TCP) voice call link buffer fully utilized service queueing delay max voice delay ANCS /29

3 ANCS /29 Table of Contents 1 Motivation 2 Problem Statement 3 Algorithm 4 Implementation 5 Evaluation 6 Wrap Up

4 ANCS /29 Table of Contents 1 Motivation 2 Problem Statement 3 Algorithm 4 Implementation 5 Evaluation 6 Wrap Up

5 ANCS /29 Rate Neutrality avoid control and accounting overhead => avoid preferential treatment of traffic use shared FIFO service as benchmark service rates proportional to arrival rates rate control at edge/end nodes: TCP, etc.

6 ANCS /29 Rate Neutrality avoid control and accounting overhead => avoid preferential treatment of traffic use shared FIFO service as benchmark service rates proportional to arrival rates rate control at edge/end nodes: TCP, etc. classical packet scheduling? absolute: needs rate allocation (signalling) priority: preferential treatment => distorts edge/end control

7 ANCS /29 Delay Control delay control without rate increase? > packet discard rate neutral with packet discard? > preserve service

8 ANCS /29 Delay Control delay control without rate increase? > packet discard rate neutral with packet discard? > preserve service proposal: multi-class queueing system maximum queueing delay per class preserve service within class throughput similar to corresponding FIFO

9 ANCS /29 Incentive Compatibility end/edge systems freely choose service class no preferential treatment lower delay = less buffer = higher loss => strategy-proof

10 ANCS /29 Incentive Compatibility end/edge systems freely choose service class no preferential treatment lower delay = less buffer = higher loss => strategy-proof not addressed: indirect effects (TCP, etc.) smaller RTT > higher sending rate enforce transparency at router? hard-code router policy for specfic e2e mechanism? sound architecture? modular design?

11 ANCS /29 Use Cases isolated deployment peering exchange, residential gateway edge-based load control IETF PCN architecture small router buffers experimentation and transition small number of (standardized) delay classes

12 ANCS /29 Conceptual Design per-class packet queues F E C D B A slot queue F E D C B A E F B A classification delay test output late delay test: worst-case linear complexity

13 ANCS /29 Alternative Conceptual Design packet discard classification packet queue rate-proportional packet scheduler rate estimation rate allocation rate estimation/allocation: complexity, accuracy, time lag

14 ANCS /29 Table of Contents 1 Motivation 2 Problem Statement 3 Algorithm 4 Implementation 5 Evaluation 6 Wrap Up

15 ANCS /29 Virtually Isolated FIFO Queueing manage FIFO queue of virtual slots virtual slot: packet in regular FIFO here: right to send at some point in time admit packet, if virtual slot available in queue with suitable service time store in packet queue (sorted by service time) purge unused virtual slots from system avoid virtual buffer hogging

16 ANCS /29 VIFQ Operation service buffer arrival DC B A

17 ANCS /29 VIFQ Operation service buffer arrival DC B A classification DC B A

18 ANCS /29 VIFQ Operation service buffer arrival DC B A classification DC B A packet/slot queue B A

19 ANCS /29 VIFQ Operation service buffer arrival DC B A classification DC B A packet/slot queue B A service B

20 ANCS /29 VIFQ Operation service buffer arrival DC B A classification DC B A packet/slot queue B A service B arrival I HGF E

21 ANCS /29 VIFQ Operation service buffer arrival DC B A classification DC B A packet/slot queue B A service B arrival I HGF E classification I HGF E

22 ANCS /29 VIFQ Operation service buffer arrival DC B A classification DC B A packet/slot queue B A service B arrival I HGF E classification I HGF E packet/slot queue I HG E F B

23 ANCS /29 Table of Contents 1 Motivation 2 Problem Statement 3 Algorithm 4 Implementation 5 Evaluation 6 Wrap Up

24 ANCS /29 Complexity in Arrival Routine two loops proportional to arriving packet length 1 purge unused slots 2 reconcile different packet lengths packet-amortized constant complexity router designed to handle minimum size packets extra CPU capacity for larger packets

25 ANCS /29 Sorted Packet Queue hardware-assisted priority queue => O(1) timer wheel with find-first-set instruction software tree/heap-based priority queue worst-case: O(logN) in small number of classes

26 ANCS /29 Table of Contents 1 Motivation 2 Problem Statement 3 Algorithm 4 Implementation 5 Evaluation 6 Wrap Up

27 ANCS /29 Simulation Parameters dumbbell topology 50 Mbit/s bottleneck 60 msec roundtrip propagation delay methodology compare throughput, utilization, etc., with FIFO verify delay differentiation

28 CBR vs. Pareto - Example 50 FIFO CBR 60 Pareto Throughput (Mbit/sec) Experiment Time (sec) ANCS /29

29 CBR vs. Pareto - Example 50 VIFQ CBR 10 Pareto Throughput (Mbit/sec) Experiment Time (sec) ANCS /29

30 CBR vs. Pareto - Example FIFO CBR 60 Pareto Max Delay (msec) Experiment Time (sec) ANCS /29

31 CBR vs. Pareto - Example VIFQ CBR 10 Pareto Max Delay (msec) Experiment Time (sec) ANCS /29

32 CBR vs. Pareto - Throughput CBR 60, Pareto 60, FIFO CBR 10, Pareto 60, VIFQ CBR Throughput (Mbit/sec) CBR Offered Load (Mbit/sec) ANCS /29

33 CBR vs. Pareto - Utilization Total Throughput (Mbit/sec) CBR 60, Pareto 60, FIFO CBR 10, Pareto 60, VIFQ CBR 10, Pareto 10, FIFO CBR Offered Load (Mbit/sec) ANCS /29

34 ANCS /29 Multiple Classes delay class traffic type 60 msec 50 long-term, greedy TCP flows 60 msec 10/sec short (web) TCP flows, 100KB 20 msec CBR, 20% load 10 msec CBR, 20% load 100 msec Pareto, 20% load 10 msec Pareto, 20% load

35 Multiple Classes - Throughput 10 FIFO 60 VIFQ Avg. Throughput (Mbit/sec) TCP 60 Web 60 CBR 20 CBR 10 Pareto 100 Pareto 10 Traffic Type ANCS /29

36 Multiple Classes - Delay 0.1 TCP 60 Web 60 CBR 20 CBR 10 Pareto 100 Pareto 10 Max Delay (msec) Experiment Time (sec) ANCS /29

37 ANCS /29 Table of Contents 1 Motivation 2 Problem Statement 3 Algorithm 4 Implementation 5 Evaluation 6 Wrap Up

38 ANCS /29 Wrap Up new approach to differentiated delay control rate neutral, incentive-compatible VIFQ concept: versatile building block VIFQ algorithm: simple and feasible initial evaluation results promising next steps: scenarios, modelling, implementation

39 ANCS /29 Extra Slides

40 TCP vs. Pareto - Throughput TCP Throughput (Mbit/sec) flow 10 flows 50 flows 100 flows TCP Delay Class (msec) ANCS /29

41 Short Flows - Completion Time VIFQ FIFO Avg. Flow Completion (sec) Shortflow Delay Target ANCS /29

42 ANCS /29 TCP/TFRC - Throughput Throughput (Mbit/sec) 50 flows TCP Del. Target TFRC Del. Target 100