Moving Forward with the IPI Photonics Roadmap

Transcription

1 Moving Forward with the IPI Photonics Roadmap TWG Chairs: Rich Grzybowski, Corning (acting) Rick Clayton, Clayton Associates

2 Integration, Packaging & Interconnection: How does the chip get to the outside world? Photonics for Consumer Products Technical, Economic, and Regulatory Drivers Handhelds (optical interconnects for cellphones, PDAs, Digital Media Players, Digital Game Consoles, etc.) Digital Home (optical links for HD video, audio, computing, automation, etc.) Packaging Needs of Consumer Photonics Roadmap for Market Penetration Industry Questionnaire Parallel optical Interconnects High density optical interconnects Survey results to-date

3 Fall 07: Key Take-Away Points (1 of 3) Off-Chip Optical Interconnects (Board-to-Board, Cabinet-to-Cabinet) Cost goal: $1/Gbps today off by a factor of 5-10, depending on volume and bit rate; easier to meet $5 for 5 Gbps link than $1 for 1 Gbps link; $5 for 5 Gbps can be achieved for volumes of Millions (no need for 100 s of Millions to hit target) Power consumption goal: 1 mw/gbps today off by a factor of ; in electronics 0.1 mw/gbps on chip and 3-4 mw/gbps off chip Multimode short-wavelength ( nm) technology is maintained up to at least 100 m (can be up to 300 m for 10 Gbps and 50 µm core) Links longer than 10 m require graded-index core Ribbons of graded index waveguides with 1 db/m loss have been done; 10 m ribbon with 10 db loss feasible, would make sense for large number of waveguides VCSELs are mostly multimode and can be directly modulated up to 10 Gbps, possibly 20 Gbps or at most 25 Gbps (at 900 s nm); 40 Gbps requires external modulation Going from 1 Gbps VCSELs to 10 Gbps VCSELs is a significant delta. Yield, packaging, and testing become more challenging. Need to change epitaxy and testing for 20 Gbps. Above 10 Gbps, it becomes harder and harder to get detectors with top-illumination, extremely low doping is needed At 40 Gbps, have to go to III-Vs and Single Mode; Single Mode allows use of Mux and Demux, so can use WDM Multilayer vs. single layer board-level optical waveguides: crossings can easily be done if single-mode, however crossing multimode waveguides is challenging, could effectively be a new type of EMI

4 Fall 07: Key Take-Away Points (2 of 3) On-Chip Optical Interconnects Single-mode links are the way to go for on-chip interconnects Single Mode allows use of Mux and demux, can use WDM Optical pins (I/O): Reducing ball size of BGA in electronic packaging can increase number of electrical pins by at least a factor of 5 (up to ~20K pins); in electronics, die stacking can be used, then edge-to-edge proximity interconnects, 100 s of thousands of interconnects are possible electrically; electronic packaging people ask if optics can deliver 1 Billion interconnects In terms of whether optics is still needed to bring signals to and from the electronic assembly: electronic designers try to avoid having the I/O become a problem by coming up with architectural solutions that hide latency; for example, a fast DRAM caching main memory with 100 MB in the package drops requirements of going off package; newer laptops have flash memory that sits in front of hard drives Optical pins are more likely to be needed for reasons other than electrical pin count limits; such reasons can be EMI or form factor

5 Fall 07: Key Take-Away Points (3 of 3) Weak Links in Optical Links Optical Link: Electrical Input Laser Driver Laser Optical Interface Optical Waveguide Optical Interface PD TIA Electrical Output Power Consumption: When VCSELs are used, the highest power consumption in an optical link is at the TIA When Edge-Emitting Lasers are used, the highest power consumption in an optical link is at the laser driver In general, an optical link needs to be designed as a whole, to balance the power consumption of elements and meet the total power consumption budget Reliability: All elements in an optical link are available with 20-year lifetime Customers care mostly about first 3-5 years Failure rates in the industry are based on random failures rates obtained from field data; 90% of failures happen at the optical interfaces (defects, dirt, chemical interactions); actives, perceived to be the main source of failures, in reality account for fewer than 10% of failures

6 HPC Box-to-Box Scenario

7 Board-to-Backplane Scenario

8 Chip-to-Chip Scenario