IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER. Research Scholar, IIT Kharagpur.
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1 Journal of Analysis and Computation (JAC) (An International Peer Reviewed Journal), ISSN Volume XI, Issue I, Jan- December 2018 IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER R.Anita 1, Dr B. Rama Rao 2, Venkatesh Vakamullu 3 1 PG Student [VLSI], Dept. of ECE, AITAM, Tekkali, A.P., India. 2 Professor, Dept. of ECE, AITAM, Tekkali, A.P., India. 3 Research Scholar, IIT Kharagpur. ABSTRACT: This work describes the implementation of generalized Multilayer Perceptron (MLP) architecture based ANN and its hardware realization using hardware description language (VHDL) on FPGA.The complete work undergoes in three phases, in the first phase, the development and training of an MLP architecture based ANN using MATLAB is done. In the Second phase, A MATLAB-SIMULINK model is created to test the network.in the third phase, the ANN SIMULINK model is implemented on FPGA using VHDL. As a part of the development, Back propagation algorithm is used for the training of ANN and the sigmoid function is used as Activation function in the network. Since the sigmoid function is nonlinear function, its realization becomes impractical on FPGA. Hence a linearly approximated sigmoid function is developed to replace the original sigmoid function. Fixed point approximation is used for the representation of network parameters and to carry out the mathematical operations on FPGA. In this work, ANN is implemented for full adder circuit as an example of general purpose application and the results of FPGA are compared with that of ANN SIMULINK model using various plots. Synthesis and simulation details of ANN on FPGA are also verified. Keywords: Artificial Neural Network, Activation Functions, Back propagation algorithm, Simulink, Verilog. [1] INTRODUCTION As the title suggests our project deals with a hardware implementation of artificial neural networks, specifically a FPGA implementation. During the course of this project we learnt about ANNs and the uses of such soft computing approaches, [3,5] FPGAs, VHDL and use of various tools like Xilinx ISE Project Navigator [1,9,11]. As numerous hardware implementations of ANNs already exist our aim was to come up with an approach that would facilitate topology evolution of the ANN as well. The key problem in the simulation of ANN s is its computational overhead. Networks containing millions of neurons and ten billion connections, and complex models like spiking neurons with temporal time course that require convolutions to be computed at each synapse, will challenge even the fastest computers [2,10]. Hence there is R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 1
2 IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER much interest in developing custom hardware for ANN s. Inherent parallelism and connectionist model of ANN s which find a natural application through hardware. General purpose processors operate sequentially. Simple ANN models require simple, low precision computations which can be performed faster on cheap and low precision hardware. Also since hardware is getting cheaper by the day, custom hardware can be built to perform complex computations. [2] NEURON ACTIVATION FUNCTION [2.1] Sigmoid Activation Function: In the hardware concept of Neural Network it is not easy to implement on FPGA, because it consists of infinite exponential series. Note that some sort of sigmoid function is often used as the nonlinear activation function, such as the logsig function shown in the following: [3] f(x) =1 / (1+e - x ) Figure 1. The Sigmoid Function [3] METHODOLOGY [3.1] Neural Network Architecture: Artificial neural networks (ANN) are a form of artificial intelligence, which have been modelled after, and inspired by the processes of the human brain. Structurally, ANNs consist of massively parallel, highly interconnected processing elements. In theory, each processing element, or neuron, is far too simplistic to learn anything meaningful on its own. [4] [3.2] Back propagation Algorithm: Figure 2. The Perceptron Model ANNs can be classified into two general types according to how they learn supervised or R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 2
3 Journal of Analysis and Computation (JAC) (An International Peer Reviewed Journal), ISSN Volume XI, Issue I, Jan- December 2018 unsupervised. The back propagation algorithm is considered to be a supervised learning algorithm, which requires a trainer to provide not only the inputs, but also the expected outputs. Basically when implementing the back propagation algorithms on FPGAs there are two approaches :Non-RTR Approach and RTR Approach. RTR stands for Run-Time- Reconfiguration. [8] Figure 3. Multilayer Perceptron [3.3] Implementation of Artificial Neural Network Using MATLAB: A full adder circuit was taken as an example of general purpose neural network and was implemented using MATLAB. Full adder circuit consists of 3 inputs and 2 outputs (sum, carry). The complete design was accomplished in two phases 1. Development of network 2.Training and simulation of the network Development of network: As a part of the development of network, a multilayer perceptron architecture based neural network was design with 3 layers. First layer is the input layer, consists of 3 input neurons, Second layer is hidden layer, consists of 10 neurons and the Third layer is the output layer consists of 2 output neurons. The following figure illustrates the architecture of neural network. Training and simulation: Once the network was established, initially the network was setup with a known set of data and random weights. Then the training was carried out for iterations. R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 3
4 IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER Figure 4. Architecture of Neural Network for full adder application Inputs Outputs X1 X2 X3 SUM CARRY Table 1. Training data of the neural network [3.4] Simulink Model of Artificial Neural Network: This model is the prototype of the network which is to be implemented on FPGA. This model consists of neurons made up of Adders multipliers and sigmoid function. The following figures show the SIMULINK model of neural. In the below figure sigmoid function was used as activation function which is nonlinear function. Implementation of the nonlinear function on FPGA is impractical. Hence the sigmoid function was approximated by linear equations. The original sigmoid function is defined as f(x) =1 / (1+e - x ) Where x is the input and f(x) is the output of the sigmoid. In the below plot the maximum MSE seen in between Original sigmoid and piecewise linearly approximated signal is 0.16%. R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 4
5 Journal of Analysis and Computation (JAC) (An International Peer Reviewed Journal), ISSN Volume XI, Issue I, Jan- December 2018 Figure 5. Piecewise linearly approximated sigmoid function and Original Sigmoid function Figure 6. Plot of sigmoid input and MSE of two sigmoid function Figure 7. SIMULINK Model of Neural Network (FULL ADDER) R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 5
6 IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER [3.5] FPGA Implementation of Neural Network Architecture of Neural Network (Full Adder): The complete neural network was implemented on FPGA, based on the prototype of SIMULINK model discussed [7]. The network mainly consists of 2 layers ( Hidden layer and output layer). Hidden layer consists of 10 neurons an output layer consists of 2 neurons. Each neuron in each layer consists of multiplication addition and sigmoid blocks. Figure 8 gives the idea of architecture of neural network. [5], [6], Figure 8. Architecture of Neural network (Full Adder) R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 6
7 Journal of Analysis and Computation (JAC) (An International Peer Reviewed Journal), ISSN Volume XI, Issue I, Jan- December 2018 Figure 9. Architecture of Hidden Neuron Figure 10. Architecture of output layer Figure 11. Piecewise Linearly Approximated Sigmoid Function Architecture R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 7
8 IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER [4] RESULTS Inputs Actual Outputs Obtained Outputs with sigmoid function Obtained Outputs with Approximated sigmoid function Error X1 X2 X3 SUM CARRY SUM CARRY SUM CARRY SUM CARRY Table 2: MATLAB simulation results of neural network with original sigmoid function and with approximated sigmoid function Figure 12. Simulation results of hidden neuron outputs Figure13. Sigmoid output R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 8
9 Journal of Analysis and Computation (JAC) (An International Peer Reviewed Journal), ISSN Volume XI, Issue I, Jan- December 2018 Figure 14. Sum and Carry outputs of neural network S No Sigmoid Input Approximated sigmoid output(theoretical) Approximated sigmoid output on FPGA Error Table 3. Comparison between sigmoid outputs S No Outputs of network with original sigmoid using Matlab Outputs of network with Approx. sigmoid using Matlab Outputs of network with Approx. sigmoid using FPGA Error SUM CARRY SUM CARRY SUM CARRY SUM CARRY Table 4: Comparisons Network outputs for various platform R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 9
10 IMPLEMENTATION OF FPGA-BASED ARTIFICIAL NEURAL NETWORK (ANN) FOR FULL ADDER [5] CONCLUSIONS The network was developed using MATLAB and tested on SIMULINK. As a part of the network a linearly piecewise approximated sigmoid (PLAS) function was developed and simulated. Various plots were drawn to compare the PLAS with original sigmoid function and the maximum error noted between them is 0.16%. The same was implemented on FPGA and compared with the theoretical values. Later the neural network was developed in VHDL using Xilinx 14.5 ISE tool and simulated results were verified. Throughout development of the network fixed point representation was used to represent the data and carry out the mathematical operation. Various simulation plots were drawn and the simulated results using Xilnx were compared with MATLAB simulations and the errors were calculated. It was noticed that maximum 0.1% error obtained and it is negligible for practical applications. REFERENCES [1] Haykins, Simon, Neural Networks A comprehensive foundation, Delhi, Pearson Prentice Hall India Bhaskar, J. A VHDL Primer, Delhi, Pearson Prentice Hall India. [2] Nichols Kristian Robert, A Reconfigurable Architecture for implementing Artificial Neural Networks on a FPGA, the Faculty of Graduate Studies, the University of Guelph [3] Andrei Dinu, Marcian Cirstea, A Digital Neural Network FPGA Direct Hardware Implementation Algorithm IEEE transactions, 2007 [4] Towards an FPGA Based Reconfigurable Computing Environment for Neural Network Implementations J. Zhu, G J. Milne, B. K. Gunthe IEEE 1999 [5] Merchant Saumil, Peterson Gregory D., Park Sang Ki, Kong Seong G., FPGA Implementation of Evolvable Block-based Neural Networks, IEEE, 2006 [6] Chan Ian D, Implementation of Artificial Neural Network on a FPGA Device, Department of Electrical and Computer Engineering, University of Auckland, Auckland, New Zealand. [7] Bhaskar Bateja Pankaj Sharma FPGA implementation of artificial neural networks, NIT Rourkela, [8] Manish Panicker1, C.Babu2 Efficient FPGA Implementation of Sigmoid and Bipolar Sigmoid Activation Functions for Multilayer Perceptrons, IOSR Journal of Engineering, [9] Bhaskar, J. A VHDL Primer, Delhi, Pearson Prentice Hall India. [10] Arroyo Ledn Marc A., Castro Arnold Ruiz, Ascencio Rakl R. Leal, An Artificial Neural Network on a Field Programmable Gate Array as a virtual sensor, /99, 1999 IEEE Transactions on Neural Networks. [11] Yamina TARIGHT, Michel HUBIN, FPGA Implementation of a Multilayer Perceptron Neural Network using VHDL, Proceedings of ICSP '9 R.Anita, Dr. B. Rama Rao and Venkatesh Vakamullu 10
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