Final Presentation. Network on Chip (NoC) for Many-Core System on Chip in Space Applications. December 13, 2017
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1 Final Presentation Network on Chip (NoC) for Many-Core System on Chip in Space Applications December 13, 2017 Dr. ir. Gerard Rauwerda
2 NoC round table Network-on-Chip (NoC) round table co-organized by ESA and CNES in 2009: future SoC developments for space applications would benefit significantly from the use of NoC technology; no NoC IP was generally available for the space community without entailing specific modifications or adaptations. (c) 2017 Recore Systems BV 2
3 Contract details ITT No.: AO/1-8166/14/NL/LF ESA Contract No.: /15/NL/LF Prime Contractor: Recore Systems BV, The Netherlands Sub-Contractor: Cobham Gaisler AB, Sweden (c) 2017 Recore Systems BV 3
4 Our objectives To propose and define Network-on-Chip technology; To propose hardening of the proposed NoC technology; To implement the NoC IP in VHDL (for SoC design); To implement functional SystemC (for early software development); To demonstrate the NoC IP capabilities implementing a reference design (use case); To validate the NoC IP using rad-hard CMOS target technology. (c) 2017 Recore Systems BV 4
5 Results NoC IP technology for future System-on-Chip (SoC) available in ESA s IP core portfolio for the European space industry; and NoC IP validated with state-of-the-art space proven IP components for hardened ASIC process technologies. (c) 2017 Recore Systems BV 5
6 Baseline Network-on-Chip Recore s NoC already used in MPPB, XentiumDARE and SSDP
7 Baseline NoC (1/2) Used in MPPB, XentiumDARE, SSDP Packet-switched routing 5 port routers 4 services, priority based for throughput and latency guarantees Memory mapped communication protocol layer X-Y routing deadlock free design-time layout of tiles based on estimated traffic load (c) 2017 Recore Systems BV 7
8 Baseline NoC (2/2) Before this activity: NoC technology integrated and part of sub-system / SoC design Fault-tolerance not integral part of NoC After this activity: NoC IP available as stand-alone IP package Including documentation, stand-alone testbench Fault-tolerance improvements (c) 2017 Recore Systems BV 8
9 Baseline NoC extensions sent p acket received packet T P H... T P H X-Y rou ting Adaptive XY-routing to provide data rerouting in the NoC Flit-level flow control Enable the insertion of EDAC on data links to increase robustness of flits (c) 2017 Recore Systems BV 9
10 NoC architecture IP IP NoC IF NI-MS R NoC IF NI-MS R Network Interface M = NoC Master S = NoC Slave IP NoC IF NI-MS Xentium 0 NI-MS IP NoC IF NI-MS IP NoC IF NI-MS R R R R Router AHB-NoC Bridge NI-MS IP NoC IF NI-MS IP NoC IF NI-MS IP NoC IF NI-MS Link R R R R IP NoC IF NI-MS IP NoC IF NI-MS Channel R R (c) 2017 Recore Systems BV 10
11 NoC protocol Transactions (1/3) NoC Master (1) initiate a transaction (2) reply package (for read) NoC Slave Each transaction is built from a couple of flits of different types (e.g., header, payload, and tail): Interrupt / Signaling Single Read Single Write (no Acknowledgement reply) Block Read Block Write (no Acknowledgement reply) Block Write with Interrupt reply (c) 2017 Recore Systems BV 11
12 NoC protocol Transactions (2/3) HOST LEON (1) Configuration + start (3) EOT interrupt (end of DMA transfer) DMA (Master) Indirect Transfer Transfer from slave-to-slave initiated by a master (2-a) Indirect transfer command Source Slave (2-b) Block write (2-c) EOT signal (end of NoC transfer) Destination Slave (c) 2017 Recore Systems BV 12
13 NoC protocol Transactions (3/3) HOST LEON (1) Configuration + start (3) EOT interrupt (end of DMA transfer) DMA (Master) Self Transfer (2-a) Indirect transfer command (source = destination) Special case of indirect transfer: source slave and destination slave is the same NoC device Example: data copy in same memory Source & Destination Slave (2-c) EOT signal (end of NoC transfer) (c) 2017 Recore Systems BV 13
14 Fault Resilience Investigations and extensions on baseline NoC
15 NoC layered architecture NoC Hardware SW higher layers transport layer network layer data Link layer network layer data link layer NoC application NoC operating system packet transmission between peers packet routing flit transmission and flow control processing elements network interfaces switches with routing functionality physical layer phy phy physical transmission of phits interconnect links Network-on-Chips layers and modules M. Radetzki, et al., Methods for Fault Tolerance in Networks on Chip, ACM Computing Surveys, 2013 (c) 2017 Recore Systems BV 15
16 Fault Model Packet Loss Packet Corruption (c) 2017 Recore Systems BV 16
17 Fault Mitigation Techniques Packet Packet Packet-Level Flow Control Mitigation techniques are proposed to be implemented in datalink and network layer. (c) 2017 Recore Systems BV 17
18 NoC improvements Robustness Error handling, error signalling embedded as side-signals in flit Static error correction Detour/rerouting of traffic in NoC also improves traffic load balance Transient error resilience FF hardening (e.g. ST65Space, DARE180) synthesis support Transient error detection / correction instantiate & integrate EDAC mechanisms on data CRC on payload EDAC flit hardening with error signalling (c) 2017 Recore Systems BV 18
19 NoC improvements Data rerouting in NoC (1/2) Xentium 0 IP X-Y routing detour from (1, 1) detour from (1, 0) X-Y Routing West-First Routing Allowed Turns Not Allowed Turns (c) 2017 Recore Systems BV 19
20 NoC improvements Data rerouting in NoC (2/2) Detour LUT registers contain modified packet header information with intermediate router coordinates Y ,3 1,3 2,3 3,3 Xentium 0 NI-MS 0,2 1,2 2,2 3,2 0,1 1,1 2,1 3,1 Xentium 0 NI configuration interface Detour look-up-table intermediate router IP NoC IF NI-MS 1,2 0 0,0 1,0 2,0 3, X (c) 2017 Recore Systems BV 20
21 NoC IP NoC IP components and testbenches
22 NoC IP components AMBA NI (NoC bridge interface) NoC router (c) 2017 Recore Systems BV 22
23 ... NoC router testbench Slave Master Slave Master Testbench Router Router... for a broken link: assert is automated generated Slave Master Router Router assert is triggered when a non-idle flit is sent through a broken link Router... Defect Map (c) 2017 Recore Systems BV 23
24 AMBA NI (c) 2017 Recore Systems BV 24
25 AMBA NI (MNI) Master Network Interface: Initiates requests on NoC to Slaves Reacts on replies from Slaves Reacts on IRQ messages from NoC NoC_Out_Irq MNI SVC0 CR SVC0 In AHB-S block_ allowed SVC123 sel_svc123 Request FSM Reply FSM SVC3 SVC2 SVC1 SVC3 SVC2 SVC1 CR Arbiter Out Arbiter Out (c) 2017 Recore Systems BV 25
26 Local Bus Arbiter (LBA) Credit Control Logic (SVC1,2,3) Slave Network Interface: AMBA NI (SNI) Reacts on requests from Master Initiates replies to Master Initiates IRQ messages on NoC SNI_wo_FC Local Bus Handler 3 (LBH) SVC3 Service Handler Input 3 (SHI) Service Handler Output 3 (SH0) noc_type_in3 noc_full_out3 noc_type_out3 noc_full_in3 Local Bus Interface Local Bus Handler 2 (LBH) Service Handler Input 2 (SHI) Service Handler Output 2 (SH0) Irq requests for unmapped memory address accesses Local Bus Handler 1 (LBH) Service Handler Input 1 (SHI) Service Handler Output 1 (SH0) Interrupt Service Handler (ISH/SVC0) Irq requests for indirect, block write w/ irq noc_type_out0 noc_full_in0 NoC_In_Irq (c) 2017 Recore Systems BV 26
27 AMBA NI test bench (c) 2017 Recore Systems BV 27
28 AMBA-NI functional verification AMBA-NI IP Configurations Full with both AHB master and slave IF Only AHB master IF (SNI - NoC2AHB) Only AHB slave IF (MNI - AHB2NoC) AMBA-NI Verification Configurations IP testbench (released with IP package) IP NoC mesh test bench (in-house) SNI IP Block test bench (in-house) (c) 2017 Recore Systems BV 28
29 NoC performance testing NoC IP performance monitoring
30 NoC event monitor NoC monitor wrapped around each router; monitors Throuhput, latency, Error Events (c) 2017 Recore Systems BV 30
31 ... NoC router testbench extension Slave Master Slave Master Testbench Router Router... Master Slave Router... Defect Map (c) 2017 Recore Systems BV 31
32 Heatmap (no detour) out 705 in out 772 in 2 in 665 out in 695 out in out in out in out out in out in out in out 562 in out 648 in 1 in 722 out in 684 out in out in out in out out in out in out in out 769 in out 629 in 0 in 744 out in 844 out (c) 2017 Recore Systems BV 32
33 Heatmap (detour for traffic balance) out 723 in out 683 in 2 in 714 out in 779 out in out in out in out out in out in out in out 614 in out 590 in 1 in 693 out in 705 out in out in out in out out in out in out in out 502 in out 551 in 0 in 643 out in 516 out (c) 2017 Recore Systems BV 33
34 Heatmap (detour broken link) out 683 in out 556 in 2 in 711 out in 711 out in out in out in out out in out in out in out 816 in out 622 in 1 in 746 out in 729 out in out in out in out out in out in out in out 287 in out 551 in 0 in 675 out in 404 out (c) 2017 Recore Systems BV 34
35 NoC reference system FPGA reference NoC implementation and multi-core software use-case
36 Master LEONEL Slave Master SpW Slave Router Router Slave Scalable 2D-mesh many-core Master LEONEL DDR Slave Router Router architecture SpaceWire element (0,0): connects GRSPW2 SpaceWire controller Memory element (0,1): AHB slave memory LEONEL (1,0): connects LEON3FT Processing Element LEONEL (1,1): connects LEON3FT Processing Element (c) 2017 Recore Systems BV 36
37 LEONEL LEONEL LEONEL Router Router Router LEONEL LEONEL LEONEL Router Router Router SpW DDR LEONEL Router Router Router (c) 2017 Recore Systems BV 37
38 LEONEL: Leon3 Processing Element (c) 2017 Recore Systems BV 38
39 Synthesis Target clock frequencies 180MHz, 500MHz and 1GHz for DARE180, ST C65SPACE and ST 28nm FD-SOI. NoC router is estimated ~25 kgates (version with all directions connected) full AMBA Network Interface is estimated ~70 kgates (full version) Reference system available for Xilinx 7-Series and Virtex-5 NoC Router: Slices / LUTs AMBANI: Slices / LUTs (c) 2017 Recore Systems BV 39
40 Test case validation software The NoC reference system includes validation software The test software uses a parallelized version of the OpenJPEG library to compress an image. The program is divided into one main control program that handles the sequential part of the code running on LEONEL0, and multiple worker programs that perform the parallel part of the work running on LEONEL1-LEONEL7. (c) 2017 Recore Systems BV 40
41 Wrapup Final results
42 ESA IP core availability NoC IP available as ESA IP core for ESA s own requirements. VHDL implementation of NoC IP SystemC model of NoC IP for early software development ASIC Synthesis scripts FPGA reference projects compatible with GRLIB with compression software use case (c) 2017 Recore Systems BV 42
43 Conclusion The activity resulted in NoC IP: NoC router AMBA-to-NoC Network Interface (AMBANI) The IP has been integrated in a reference design The IP can be synthesized and targetted to different ASIC and FPGA technologies Performance tools are integrated in the NoC mesh testbench SystemC models for early software development are available (c) 2017 Recore Systems BV 43
44 GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O Ready for the next step? Heterogeneous many-core SoC Xentium VLIW DSP core in rad.-hard 65nm CMOS Clock: 300 MHz Performance: 1.8 GFLOPs/s NoC per link: 9.6 Gbit/s Area: 1.1 mm 2 75% gates utilization Including NoC interface Many-core SoC example 48 Xentium processing tiles 16 memory tiles 60 NoC routers 8 8 mesh 60 Giga MACs/s 90 GFLOPs/s GPP 1 GPP 2 SRAM SRAM I/O I/O I/O I/O bridge bridge bridge bridge bridge bridge bridge bridge bridge GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O bridge bridge bridge bridge bridge bridge bridge bridge DAC ADC Bridge to analogue front-end 1 Bridge to analogue front-end 2 (c) 2017 Recore Systems BV 44
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