HAI ZHOU. Evanston, IL Glenview, IL (847) (o) (847) (h)

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1 HAI ZHOU Electrical and Computer Engineering Northwestern University 2535 Happy Hollow Rd. Evanston, IL Glenview, IL (847) (o) (847) (h) EDUCATION Ph.D. University of Texas at Austin May Major: Computer Sciences Thesis: Signal Integrity and Low Power Issues in Deep Sub-Micron VLSI Design Advisor: Professor Martin D. F. Wong M.S. Tsinghua University, Beijing, China June Major: Computer Science and Technology Thesis: OOUID An Object-Oriented User Interface Design Tool Advisor: Professor Xingliang Lin B.S. Tsinghua University, Beijing, China June Major: Computer Science and Technology Minor: Management GPA: 91/100 ranked second in graduating class (161 students) HONORS AND AWARDS CAREER Award National Science Foundation, Special Recognition Award Synopsys, Inc., 2000 Motorola Scholarship (top 5%) Tsinghua University, 1993 Guanghua Scholarship (top 5%) Tsinghua University, 1992 Third rank Mathematics Competition, Tsinghua University, 1990 Top 100 National Physics Olympiad, China, 1986 WORKING EXPERIENCE Sep 2001 present: Assistant Professor, Electrical and Computer Engineering, Northwestern University.

2 Jun 1999 Aug 2001: Senior R&D Engineer, Advanced Technology Group, Synopsys Inc. Aug 1994 May 1999: Research/Teaching Assistant, Department of Computer Sciences, Department of Electrical and Computer Engineering, The University of Texas at Austin. Jun 1997 Aug 1997: Summer Intern, Placement and Route Group, Avant! Corporation, Fremont, CA. PROFESSIONAL SERVICES Technical Program Committee of ICCAD: IEEE International Conference on Computer Aided Design Technical Program Committee of ICCD: IEEE International Conference on Computer Design Technical Program Committee of GLS-VLSI Technical Program Committee of Tau 2004: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. Technical Program Committee of ICCAD: IEEE International Conference on Computer Aided Design NSF Panelist for Design Automation Program Publications Chair of ACM Great Lake Symposium on VLSI Session Chair of ISCAS: IEEE International Symposium on Circuits and Systems Session chair of ISPD: ACM International Symposium on Physical Design 2001, Technical Program Committees of ISPD: ACM International Symposium on Physical Design 2001, 2002 STUDENTS PhD Students: Chuan Lin, Debjit Sinha, Ruiming Chen, Jia Wang PUBLICATIONS Book chapter 1. H.-M. Chen, D. F. Wong, H. Zhou, F. Y. Young, H. H. Yang, and N. Sherwani. Integrated Floorplanning and Interconnect Planning. Layout Optimizations in VLSI Designs, D.-Z. Du, S. Sapatnekar, and B. Lu eds., Kluwer Academic Publishers. To appear.

3 Journal articles 2. H. Zhou and D. F. Wong. Optimal River Routing with Crosstalk Constraints. ACM Transactions on Design Automation of Electronic Systems, July H. Zhou and D. F. Wong. Global Routing with Crosstalk Constraints. IEEE Transactions on Computer-Aided Design, 18(11), November, H. Zhou, D. F. Wong, I-M. Liu, and A. Aziz. Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. IEEE Transactions on Computer-Aided Design, 19(7), July, H. Zhou and A. Aziz. Buffer Minimization in Pass Transistor Logic. IEEE Transactions on Computer-Aided Design, 20(5), May, H. Zhou, N. Shenoy, and W. Nicholls. Efficient Minimum Spanning Tree Construction without Delaunay Triangulation. Information Processing Letters, Vol. 81, No. 5, A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal. BDD-based Procedures for a Theory of Equality with Uninterpreted Functions. Journal of Formal Methods in System Design, 22(3), pp , May H. Zhou. Timing Analysis with Crosstalk is a Fixpoint on a Complete lattice. IEEE Transactions on Computer-Aided Design, 22(9), pp , Sept H. Zhou. Efficient Steiner Tree Construction Based on Spanning Graphs. IEEE Transactions on Computer-Aided Design, 23(5), pp , May H. Zhou and C. Lin, Retiming for Wire Pipelining in System-On-Chip. IEEE Transactions on Computer-Aided Design, Sept Conference papers 11. H. Zhou and D. F. Wong. An Optimal Algorithm for River Routing with Crosstalk Constraints. In International Conference on Computer Aided Design, San Jose, CA, November C.-P. Chen, H. Zhou, and D. F. Wong. Optimal Non-uniform Wire-sizing under the Elmore Delay Model. In International Conference on Computer Aided Design, San Jose, CA, November H. Zhou and D. F. Wong. An Exact Gate Decomposition Algorithm for Low-power Technology Mapping. In International Conference on Computer Aided Design, San Jose, CA, November H. Zhou and D. F. Wong. Crosstalk Constrained Maze Routing Based on Lagrangian Relaxation. In IEEE International Conference on Computer Design, Austin, TX, October 1997.

4 15. H. Zhou and D. F. Wong. Global Routing with Crosstalk Constraints. In ACM Design Automation Conference, San Francisco, CA, June A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal. BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. In International Conference on Computer Aided Verification, Vancouver, British Columbia, June H. Zhou, V. Singhal, and A. Aziz. How Powerful is Retiming? In International Workshop on Logic Synthesis, Lake Tahoe, CA, May I.-M. Liu, T.-H. Liu, H. Zhou, and A. Aziz. Simultaneous PTL Buffer Insertion and Sizing for Minimizing Elmore Delay. In International Workshop on Logic Synthesis, Lake Tahoe, CA, May H. Zhou, D. F. Wong, I-M. Liu, and A. Aziz. Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. In ACM Design Automation Conference, New Orleans, LA, June I-M. Liu, A. Aziz, D. F. Wong, and H. Zhou. An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. In IEEE International Conference on Computer Design, Austin, TX, October H.-M. Chen, H. Zhou, F. Y. Young, D. F. Wong, H. H. Yang, and N. Sherwani. Integrated Floorplanning and Interconnect Planning. In IEEE International Conference on Computer Aided Design, San Jose, CA, November H. Zhou and A. Aziz. Buffer Minimization in Pass Transistor Logic. In International Symposium on Physical Design, San Diego, CA, April H. Zhou and D. F. Wong. Optimal Low Power XOR Gate Decomposition. In ACM Design Automation Conference, Los Angeles, CA, June H. Zhou, N. Shenoy, and W. Nicholls. Efficient Minimum Spanning Tree Construction without Delaunay Triangulation. In Asian and South Pacific Design Automation Conference, Yokohama, Japan, January H. Zhou, N. Shenoy, and W. Nicholls. Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. In ACM Design Automation Conference, Las Vegas, NV, June S. H. Batterywala, N. Shenoy, W. Nicholls, and H. Zhou. Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing. In IEEE International Conference on Computer Aided Design, San Jose, CA, H. Zhou. Clock Schedule Verification with Crosstalk. In Tau 02: ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, CA, C. W. Sham, F. Y. Young, and H. Zhou. Interconnect-Driven Floorplanning by Searching Alternative Packings. In Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, 2003.

5 29. H. Zhou. Timing Verification with Crosstalk for Transparently Latched Circuits. In DATE 03: Design Automation & Test in Europe, Munich, Germany, H. Zhou. Efficient Steiner Tree Construction Based on Spanning Graphs. In ACM International Symposium on Physical Design, Monterey, CA, C. Lin and H. Zhou. Retiming for Wire Pipelining in System-On-Chip. In IEEE International Conference on Computer Aided Design, San Jose, CA, (Nominated for best paper award) 32. Q. Zhu, H. Zhou, T. Jing, X. Hong, Y. Yang, Efficient Octilinear Steiner Tree Construction Based on Spanning Graphs. In Asia and South Pacific Design Automation Conference, Yokohama, Japan, C. Lin and H. Zhou, Wire Retiming for System-On-Chip by Fixpoint Computation. In DATE 04: Design Automation & Test in Europe, Paris, France, D. Sinha, H. Zhou, C.C.N. Chu, Optimal Gate Sizing for Coupling-Noise Reduction. In ACM International Symposium on Physical Design, Phoenix, AZ, J. Wang and H. Zhou, Minimal Period Retiming under Process Variations. In ACM Great Lakes Symposium on VLSI, Boston, MA, H. Zhou, A New Efficient Retiming Algorithm Derived by Formal Manipulation. In International Workshop on Logic Synthesis, Temecula, CA, 2004.