Scheduling Data Flows using DRR

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1 CS/CoE 535 Acceleration of Networking Algorithms in Reconfigurable Hardware Prof. Lockwood : Fall Scheduling Data Flows using DRR Todd Sproull, Sarang Dharmapurikar and Praveen Krishnamurthy CS/CoE 535 Acceleration of Algorithms in Hardware 1 Project Background Context Provide efficient scheduling and fairness to the various data flows Why scheduling problem? Scheduling is done to provide efficient and fair use of the available bandwidth among the various flows Parameterized scheduling can be used to provide priorities to the flows in the system, depending on the need of the system The above ensures QoS in certain conditions (e.g realtime applications) CS/CoE 535 Acceleration of Algorithms in Hardware 2

2 Project Background Cont. Why DRR? Makes scheduling decision based on packet sizes and not on the number of bytes in the Queue Prevents unreasonable sources from starving the good ones More efficient than Round Robin Uses of DRR Low Cost Implementation Scalable Can be used to prioritize a particular or a set of flows to assure certain QoS CS/CoE 535 Acceleration of Algorithms in Hardware 3 Objective Use Deficit Round Robin(DRR) scheduling for providing desired fairness in a multi-flow system Implement a scalable DRR module to handle a large number of flows Efficiently enqueue cells from SAR d Inputs Inputs to the system is a multiplexed sets of cells Cells arrive in-order for each flow Cells are en-queued according to their Virtual Output Queues (VoQ) Improve throughput of a Read and Write operations from the SDRAM Decrease the latency between requests granted for the same flow Develop a NCHARGE like interface to monitor and provide inputs to the system Use control cells to check the current state of the Queues Control Cells to change the Quanta associated with the flows CS/CoE 535 Acceleration of Algorithms in Hardware 4

3 Final Project Block Diagram WRITE PROCESS SDRAM READ PROCESS Pkt FIFO 0 - Control Pkts Packet FIFO 1 WRITE BUFFER SAR Logic PULL CELL BLOCK RAM Packet FIFO (N-1) QUEUE PKT ID LEN Packet Request QUEUE FIFO (N) ID ACK REQ DRR Module CS/CoE 535 Acceleration of Algorithms in Hardware 5 Data Formats Data Inputs Control cell format Check Status Changing DRR Quantum Data Outputs Reassembled AAL5 frames Control cells Opcode Incremented Queue lengths (Status) CS/CoE 535 Acceleration of Algorithms in Hardware 6

4 Major Components Modules SAR Module MultiQueueCellFIFO DRR Module CS/CoE 535 Acceleration of Algorithms in Hardware 7 Final Project Block Diagram WRITE PROCESS SDRAM READ PROCESS Pkt FIFO 0 - Control Pkts Packet FIFO 1 WRITE BUFFER SAR Logic PULL CELL BLOCK RAM Packet FIFO (N-1) QUEUE PKT ID LEN Packet Request QUEUE FIFO (N) ID ACK REQ DRR Module CS/CoE 535 Acceleration of Algorithms in Hardware 8

5 Major Components (Contd..) SAR Module Function Schematic SAR BLOCK Data Interface Inputs : Multiplexed ATM Cells Outputs : Reassembled AAL5 Frames Name of person responsible Sarang Dharmapurikar CS/CoE 535 Acceleration of Algorithms in Hardware 9 Major Components (Contd..) MultiQueueCellFIFO Module Function Schematic - Cells are queued are based on VCs - Cells are dequeued as frames Pkt FIFO 0 - Control Pkts Packet FIFO 1 Data Interface Inputs : ATM Cells Outputs : AAL5 Frames Packet FIFO (N-1) Packet FIFO (N) Name of person responsible Sarang Dharmapurikar CS/CoE 535 Acceleration of Algorithms in Hardware 10

6 Major Components (Contd..) DRR Module Function Schematic REQ Change Quantum CTS ACK DRR Module Data Interface Inputs : PktLen, QueueID, ChangeQuantum, NewQuantum, QuantumID, Ack Outputs : ReadRequest, QueueID, Name of person responsible Praveen Krishnamurthy CS/CoE 535 Acceleration of Algorithms in Hardware 11 Major Components (Contd..) DRR Operation Append Request - Flows are appended to the Active list Check Eligibility - Compare Deficit and PktLen to check ability to send Read Request for each Queue in Active List - If Eligible append the queueid to the ready list and decrement Deficit Send Request Send new request after the last one is serviced (ack) Append Eligible? ReadyList ACK? CS/CoE 535 Acceleration of Algorithms in Hardware 12

7 Status Report VHDL Testing is complete All components tested and verified Post Synthesis testing complete Place and route in hardware needs to completed CS/CoE 535 Acceleration of Algorithms in Hardware 13 Software Java Applet GUI Interface allows for easy management of DRR Queuing Circuit Java Applet displays relevant information about the queue and allows the user to modify flow quantums CS/CoE 535 Acceleration of Algorithms in Hardware 14

8 Software Control Cells are issued by the applet over a TCP Socket to NCHARGE 3 Fields for each Queue Valid Bit Queue ID (Status) Quantum CS/CoE 535 Acceleration of Algorithms in Hardware 15 Results What does it really do? Improves throughput Provides weighted fairness How fast does it go? 40 MHz How did you test it? Post Synthesis Testing CS/CoE 535 Acceleration of Algorithms in Hardware 16

9 Throughput Results Improved Throughput = 1.41 GBps CS/CoE 535 Acceleration of Algorithms in Hardware 17 Throughput Results Worst case throughput = 0.9 Gbps CS/CoE 535 Acceleration of Algorithms in Hardware 18

10 DRR Performance Case 1: Equal Bandwidth Share CS/CoE 535 Acceleration of Algorithms in Hardware 19 DRR Performance Case 2: Prioritized Flows (VCI 1 = 4x,VCI 2 =3x, VCI 3 = 1x) CS/CoE 535 Acceleration of Algorithms in Hardware 20

11 DRR Performance Case 3: Setting Priorities at Runtime (VCI 1 = 5x,VCI 2 =4x, VCI 3 = 1x) Change Qauntas CS/CoE 535 Acceleration of Algorithms in Hardware 21 References Relevant References M. Shreedhar and G. Varghese, "Efficient fair queuing using deficit round robin," Proc. of ACM SIGCOMM '95, Aug What reusable components did you use? SDRAM controller Block RAM FIFO (Xilinx CoreGen) What new components did you implement? DRR Module Enhanced Multi Queue FIFO SAR Module GUI Control Interface CS/CoE 535 Acceleration of Algorithms in Hardware 22

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