Network-on-Chip Micro-Benchmarks
|
|
- Kelly Preston
- 6 years ago
- Views:
Transcription
1 Network-on-Chip Micro-Benchmarks Zhonghai Lu *, Axel Jantsch *, Erno Salminen and Cristian Grecu * Royal Institute of Technology, Sweden Tampere University of Technology, Finland Abstract University of British Columbia, Canada The rapid development of Network-on-Chip (NoC) calls for a systematic approach to evaluate and fairly compare various NoC architectures. In this specification, we define a generic NoC architecture, a comprehensive set of synthetic workloads as micro-benchmarks, workload scenarios and evaluation criteria. These micro-benchmarks enable measuring particular properties of NoC architectures, complementing application benchmarks. Keywords: Network-on-Chip, Performance Evaluation, Benchmark Introduction Network-on-Chip (NoC) has been recognized as a promising architecture to accommodate tens, hundreds or even thousand of cores. As a result, a number of NoC architectures have been and are being proposed. On one hand, this diversity offers designers a large selection of possibilities. On the other hand, this raises an urgent need to fairly evaluate and compare different NoC architectures in order to assist designers in making right decisions and to further advance and accelerate the state-of-the-art. Classic benchmarks for multiprocessor systems, for example, SPEC [1] and E3S [2], are application-oriented, and cannot be used directly for communication-intensive architecture such as NoCs. Moreover, the nature of the applications running on NoCbased designs is expected to be more varied and heterogeneous compared to typical applications for multiprocessor computers. To complement application benchmarks, OCP-IP has initiated a NoC benchmark endeavor [3], one part of which are NoC microbenchmarks. While benchmark programs evaluate the combined effect of many aspects of the platform as well as of the application, micro-benchmarks isolate individual properties and allow for a faster and deeper point analysis. Micro-benchmarks define synthetic workloads intending to exercise a NoC in a specific way or measure a single particular aspect. Hence, a measurement offers insight in a specific property and facilitates the analysis and design of a communication infrastructure. A single micro-benchmark provides only a very limited view and does not allow for far reaching conclusions about the suitability for an application domain. However, a set of well designed micro-benchmarks can give both a broad and detailed understanding of a given communication network. 1
2 Architecture Definition Figure 1. A NoC model with four nodes NoC features a network as a global interconnect integrating various resources, such as processors, memory, configurable or dedicated logic blocks, or local bus-based subsystems. We exemplify the NoC model to be evaluated in Figure 1, which shows four nodes connected by a packet-switched network. A node consists of a Resource Model (RM), a Network Interface (NI) and a Router (R). In our context, a resource is attached to exactly one NI, which in turn connects to exactly one router. However, a router may have no NI and RM connected to it in the case of indirect networks. The NI provides hardware interconnect interface implementing an existing on-chip communication protocol, such as OCP, AXI etc. Transactions are initiated by RMs, packetized into packets in NIs, and depacketized back into transactions after network delivery, which are received by RMs. No assumptions are made about network attributes such as topology, routing algorithm, switching policy and flow control scheme. The network may offer two classes of communication services: best-effort (BE) and guaranteed service (GS). The BE service is connection-less, delivering packets as soon as possible. The guaranteed service is connection-oriented, providing certain bounds in latency and/or bandwidth. The network reserves resources such as buffers and link bandwidth for connections. The NIs manage connections in terms of setup, configuration and tear down. The evaluation is concerned with the network and NIs including the interconnect interface. The scope of evaluation is solely on unicast communication. 2
3 Traffic Configuration Micro-benchmarks differentiate between temporal and spatial traffic distributions. Temporal distribution The temporal distribution determines how an individual RM generates traffic over time. This is based on the b-model [4] by which the burstiness of traffic generation can be controlled by a single parameter b in the range 0 < b 0.5. In the b-model, a bias parameter b = 0.4 means that, within a given time interval, 40% of the data are generated in one half of the time interval and the remaining 60% in the other half, and this continues recursively until reaching the time resolution. When b = 0.5, there is no burstiness and the emission probability is constant. The burstiness increases as b is approaching 0, Spatial distribution The spatial distribution governs the spatial property of a traffic pattern: who communicates with whom. Assuming N nodes in the network, the following spatial distributions are covered: 1. Uniform: In this classic case the probability to send a packet from one node to 1 another node is. A node does not send data to itself. N 1 2. Local: The probability to send a packet to a destination node depends on the source-destination distance. 3. Bit Rotation: a bit permutation pattern in which a given source node sends data only to one destination node whose address is obtained by rotating the bit string representation of the source node address to the right by one. 4. N-Complement: Similarly to Bit Rotation, this scenario creates load on sourcedestination pairs. Suppose that nodes are numbered as naturals 1, 2,... N, if a source node address is n s, its destination address is n d such that ns + n d = N. 5. Hot Spot: This scenario selects M of the N nodes as hot spots. A certain fraction of traffic is targeted to these hot-spots. One hot-spot is selected at a time by uniform random selection. 3
4 6. Fork-Join Pipeline: it is a pattern where a fork node feeds c nodes that are the starting point of c parallel pipelines. Each pipeline has a depth of e nodes. At the end of the pipelines after e stages, the data is merged into a join node. Measurement We consider different workload scenarios, for which we define measurement metrics. Workload type For best-effort services, we consider three workload types: packets at the network level and read/write transactions at the application level. The length of a read/write transaction may vary from a byte to a few words. For guaranteed services, we examine another three workload types: open connection, close connection and message. Here, message is the data transmitted over connections. Workload cases and metrics We differentiate unloaded and loaded cases, for which we define the following measurement metrics. Service BE GS Workload type Packet Read 2/4/8 Write 2/4/8 Open connection Close connection Message 4/16/32/128 Delay [ns or cycles] Throughput [Mbits/s] Energy [pj] Min. Avg. Max. Min. Avg. Max. Min. Avg. Max. Table 1. Evaluation criteria for the unloaded case In the unloaded case, individual packets or transactions are injected/initiated and measured so that only a single traffic source is active. This yields minimum delay and peak performance. These values may vary depending on the location of the source. Therefore, determining the minimum, average, and maximum values require several measurements. Table 1 shows the performance metrics for the loaded case. 4
5 Service Workload type Avg. Delay [ns or cycles] D 1 D2 D 3 Dn Avg. Jitter J 1 J 2 J n Θ s [Mbits/s] Energy [pj] BE GS Packet Read 2/4/8 Write 2/4/8 Open connection Close connection Message 4/16/32/128 Table 2. Evaluation criteria for the loaded case The loaded case investigates the network behavior when many independent packets or transactions compete for the same resources, and congestion, arbitration, buffering and flow control policies are exercised. Sometimes part of the load in the network may be generated as background traffic with some other micro-benchmark than the one used for measurements, for example, the uniform traffic. In the presence of congestion the network typically does not exhibit a deterministic delay behavior, we therefore also capture both delay and delay variations. Table 2 shows the performance metrics for the loaded case, where Θ s represents sustained throughput. Di / J i is the delay/jitter bound i for 1 10 of data. For instance, D / J, D / J, D / J bounds 90%, 99.9%, 99.99% of all packets or transactions, respectively. Interference of resource reservation on BE traffic To study the impact of resource allocation by guaranteed services on BE traffic, a set of micro-benchmarks shall measure the BE traffic performance when a given portion of the bandwidth of each link in the network is allocated to a guaranteed service. Network scalability Besides performance and power metrics, scalability is an important quality metric. To evaluate the scalability of NoCs, a range of network sizes can be specified as an input to the micro-benchmarks. 5
6 The Micro-Benchmark Set Each micro-benchmark has a name which reflects its function. The names have the following format: NoCmb_TEMP_SPAT_LUL_WORKLOAD_GS_SIZE_MP Fields: NoCmb: constant string suffix standing for NoC micro-benchmark. TEMP: temporal distribution. Besides burstiness, different average emission probabilities may be supplied. SPAT: spatial distribution. LUL: workload case, either LOADED or UNLOADED. WORKLOAD: workload type. GS: fraction of bandwidth reserved for the guaranteed service. SIZE: number of network nodes. MP: measurement point indicating where the performance is measured, Raw or Buffered. The Raw delay measures the delay in the network. The Buffered delay includes source queuing delay plus the RAW delay. 7 Hence, a complete set of micro-benchmarks may contain up to n micro-programs, if each field has n options. Each combination of the fields is a micro-benchmark. We give five examples: 1. NoCmb_Burst0.3Avg0.5_BitRotation_UNLOADED_Packet_GS[0,0.2,0.3,0.5]_S ize16_raw: This unloaded case creates best-effort packets with burstiness 0.3 and average probability 0.5 to bit-rotated destination nodes in a 16-node network when 0%, 20%, 30% and 50% percent of network bandwidth is reserved by the guaranteed service. Raw delay is to be measured. 2. NoCmb_Burst[0.5,0.4,0.3,0.2]Avg0.4_Uniform_LOADED_Packet_GS0_Size64_ RAW: This loaded case creates uniformly distributed best-effort packets on a 64- node network with burstiness b = 0.5, 0.4, 0.3 and 0.2, average probability NoCmb_Burst0.4Avg0.4_Uniform_LOADED_Packet_GS0_Size[4,16,64,128,25 6]_RAW: This loaded case creates uniformly distributed best-effort packets with 6
7 burstiness 0.4 and average probability 0.4 on networks with the number of nodes being 4, 16, 64, 128 and NoCmb_Burst0.3Avg0.05_BitRotation_UNLOADED_OpenConnection_GS[0,0. 2,0.3,0.5]_Size32_RAW: This unloaded case creates open-connection packets with burstiness 0.3 and average probability 0.05, to bit-rotated destination nodes in a 32-node network when 0%, 20%, 30% and 50% percent of network bandwidth is reserved by the guaranteed service. 5. NoCmb_Burst0.2Avg[0.2,0.3,0.4,0.5,0.6,0.7]_Uniform_LOADED_Packet_GS0_ Size64_Buffered: This loaded case creates uniformly distributed best-effort packets on a 64-node network with burstiness 0.2 and average probability ranging from 20% to 70% with a step length 10%. Buffered delay is to be measured. The micro-benchmarks may be implemented in different modeling or programming languages such as VHDL/Verilog, C/C++/SystemC. NoC Working Group at OCP-IP aims to provide an open source implementation of the micro-benchmarks in SystemC. Concluding Remark We have specified a rich set of micro-benchmarks to evaluate and compare NoC architectures. It will systematically exercise a set of important aspects of a NoC. It will give the NoC developer insight and guidelines for improvement. It will also give the NoC user a detailed understanding of the NoC behavior, its strengths and weaknesses. We envision that this set of micro-benchmarks will continue to evolve together with increasing endeavors in NoC activities. Acknowledgment Developing the NoC micro-benchmarks is a persistent effort of the NoC Working Group at OCP-IP. The authors would like to thank all members for their helpful discussions and insightful comments. References [1] The Standard Performance Evaluation Corporation, SPEC, [2] R. Dick, Embedded System Synthesis Benchmarks Suites (E3S) 7
8 [3] Cristian Grecu, Andre Ivanov, Partha Pande, Axel Jantsch, Erno Salminen, Umit Ogras, and Radu Marculescu. Towards open network-on-chip benchmarks. In Proceedings of First International Symposium on Networks-on-Chip, 2007 [4] Mengzhi Wang, T. Madhyastha, Chan Ngai Hang, S. Papadimitriou, and C. Faloutsos. Data mining meets performance evaluation: fast algorithms for modeling bursty traffic. In Proceedings of the 18 th International Conference on Data Engineering,
Standards for NoC: What can we gain?
Standards for NoC: What can we gain? Axel Jantsch Royal Institute of Technology, Stockholm March 2006 March 2006 Standards for NoC 1 What Kind of Standards Informal Standards are a set of assumptions shared
More informationTowards Open Network-on-Chip Benchmarks
Towards Open Network-on-Chip Benchmarks Cristian Grecu 1, Andrè Ivanov 1, Partha Pande 2, Axel Jantsch 3, Erno Salminen 4, Umit Ogras 5, Radu Marculescu 5 1 University of British Columbia, 2 Washington
More informationInterconnection Networks: Topology. Prof. Natalie Enright Jerger
Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design
More informationThe Nostrum Network on Chip
The Nostrum Network on Chip 10 processors 10 processors Mikael Millberg, Erland Nilsson, Richard Thid, Johnny Öberg, Zhonghai Lu, Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004
More informationJoint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals
Joint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals Philipp Gorski, Tim Wegner, Dirk Timmermann University
More informationAn Analysis of Blocking vs Non-Blocking Flow Control in On-Chip Networks
An Analysis of Blocking vs Non-Blocking Flow Control in On-Chip Networks ABSTRACT High end System-on-Chip (SoC) architectures consist of tens of processing engines. These processing engines have varied
More informationTopologies. Maurizio Palesi. Maurizio Palesi 1
Topologies Maurizio Palesi Maurizio Palesi 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and
More informationLecture 3: Topology - II
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 3: Topology - II Tushar Krishna Assistant Professor School of Electrical and
More informationNetwork-on-chip (NOC) Topologies
Network-on-chip (NOC) Topologies 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and performance
More informationCross Clock-Domain TDM Virtual Circuits for Networks on Chips
Cross Clock-Domain TDM Virtual Circuits for Networks on Chips Zhonghai Lu Dept. of Electronic Systems School for Information and Communication Technology KTH - Royal Institute of Technology, Stockholm
More informationPhastlane: A Rapid Transit Optical Routing Network
Phastlane: A Rapid Transit Optical Routing Network Mark Cianchetti, Joseph Kerekes, and David Albonesi Computer Systems Laboratory Cornell University The Interconnect Bottleneck Future processors: tens
More informationOverlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH
Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Outline Introduction Overview of WiNoC system architecture Overlaid
More informationBandwidth Aware Routing Algorithms for Networks-on-Chip
1 Bandwidth Aware Routing Algorithms for Networks-on-Chip G. Longo a, S. Signorino a, M. Palesi a,, R. Holsmark b, S. Kumar b, and V. Catania a a Department of Computer Science and Telecommunications Engineering
More informationA Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing
727 A Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing 1 Bharati B. Sayankar, 2 Pankaj Agrawal 1 Electronics Department, Rashtrasant Tukdoji Maharaj Nagpur University, G.H. Raisoni
More information4. Networks. in parallel computers. Advances in Computer Architecture
4. Networks in parallel computers Advances in Computer Architecture System architectures for parallel computers Control organization Single Instruction stream Multiple Data stream (SIMD) All processors
More informationCSCD 433/533 Advanced Networks Spring Lecture 22 Quality of Service
CSCD 433/533 Advanced Networks Spring 2016 Lecture 22 Quality of Service 1 Topics Quality of Service (QOS) Defined Properties Integrated Service Differentiated Service 2 Introduction Problem Overview Have
More informationFCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture
More informationOn Topology and Bisection Bandwidth of Hierarchical-ring Networks for Shared-memory Multiprocessors
On Topology and Bisection Bandwidth of Hierarchical-ring Networks for Shared-memory Multiprocessors Govindan Ravindran Newbridge Networks Corporation Kanata, ON K2K 2E6, Canada gravindr@newbridge.com Michael
More informationRouting Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip
Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip Nauman Jalil, Adnan Qureshi, Furqan Khan, and Sohaib Ayyaz Qazi Abstract
More informationPerformance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
erformance Evaluation of robe-send Fault-tolerant Network-on-chip Router Sumit Dharampal Mediratta 1, Jeffrey Draper 2 1 NVIDIA Graphics vt Ltd, 2 SC Information Sciences Institute 1 Bangalore, India-560001,
More informationFuzzy Flow Regulation for Network-on-Chip based Chip Multiprocessor System
Fuzzy Flow egulation for Network-on-Chip based Chip Multiprocessor System Yuan Yao and Zhonghai Lu KTH oyal Institute of Technology, Stockholm 14 th AS-DAC Conference 19-23, January, 2014, Singapore Outline
More informationOn the Performance Characteristics of WLANs: Revisited
On the Performance Characteristics of WLANs: Revisited S. Choi,, K. Park and C.K. Kim Sigmetrics 2005 Banff, Canada Presenter - Bob Kinicki Advanced Computer Networks Fall 2007 Outline Introduction System
More informationEE/CSCI 451: Parallel and Distributed Computation
EE/CSCI 451: Parallel and Distributed Computation Lecture #11 2/21/2017 Xuehai Qian Xuehai.qian@usc.edu http://alchem.usc.edu/portal/xuehaiq.html University of Southern California 1 Outline Midterm 1:
More informationConnection-oriented Multicasting in Wormhole-switched Networks on Chip
Connection-oriented Multicasting in Wormhole-switched Networks on Chip Zhonghai Lu, Bei Yin and Axel Jantsch Laboratory of Electronics and Computer Systems Royal Institute of Technology, Sweden fzhonghai,axelg@imit.kth.se,
More informationDynamic Flow Regulation for IP Integration on Network-on-Chip
Dynamic Flow Regulation for IP Integration on Network-on-Chip Zhonghai Lu and Yi Wang Dept. of Electronic Systems KTH Royal Institute of Technology Stockholm, Sweden Agenda The IP integration problem Why
More informationNetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013
NetSpeed ORION: A New Approach to Design On-chip Interconnects August 26 th, 2013 INTERCONNECTS BECOMING INCREASINGLY IMPORTANT Growing number of IP cores Average SoCs today have 100+ IPs Mixing and matching
More informationMatrox Imaging White Paper
Reliable high bandwidth video capture with Matrox Radient Abstract The constant drive for greater analysis resolution and higher system throughput results in the design of vision systems with multiple
More informationDesign and Implementation of Multistage Interconnection Networks for SoC Networks
International Journal of Computer Science, Engineering and Information Technology (IJCSEIT), Vol.2, No.5, October 212 Design and Implementation of Multistage Interconnection Networks for SoC Networks Mahsa
More informationTopology basics. Constraints and measures. Butterfly networks.
EE48: Advanced Computer Organization Lecture # Interconnection Networks Architecture and Design Stanford University Topology basics. Constraints and measures. Butterfly networks. Lecture #: Monday, 7 April
More informationSupporting Distributed Shared Memory. Axel Jantsch Xiaowen Chen, Zhonghai Lu Royal Institute of Technology, Sweden September 16, 2009
Supporting Distributed Shared Memory Axel Jantsch Xiaowen Chen, Zhonghai Lu Royal Institute of Technology, Sweden September 16, 2009 Memory content in today s SoCs 3 Elements in SoC Processing: Well understood;
More informationFault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies. Mohsin Y Ahmed Conlan Wesson
Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies Mohsin Y Ahmed Conlan Wesson Overview NoC: Future generation of many core processor on a single chip
More informationReal-Time Protocol (RTP)
Real-Time Protocol (RTP) Provides standard packet format for real-time application Typically runs over UDP Specifies header fields below Payload Type: 7 bits, providing 128 possible different types of
More informationApplying the Benefits of Network on a Chip Architecture to FPGA System Design
white paper Intel FPGA Applying the Benefits of on a Chip Architecture to FPGA System Design Authors Kent Orthner Senior Manager, Software and IP Intel Corporation Table of Contents Abstract...1 Introduction...1
More informationAchieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation
More informationReal Time NoC Based Pipelined Architectonics With Efficient TDM Schema
Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema [1] Laila A, [2] Ajeesh R V [1] PG Student [VLSI & ES] [2] Assistant professor, Department of ECE, TKM Institute of Technology, Kollam
More informationIV. PACKET SWITCH ARCHITECTURES
IV. PACKET SWITCH ARCHITECTURES (a) General Concept - as packet arrives at switch, destination (and possibly source) field in packet header is used as index into routing tables specifying next switch in
More informationA Novel Energy Efficient Source Routing for Mesh NoCs
2014 Fourth International Conference on Advances in Computing and Communications A ovel Energy Efficient Source Routing for Mesh ocs Meril Rani John, Reenu James, John Jose, Elizabeth Isaac, Jobin K. Antony
More informationFast-Response Multipath Routing Policy for High-Speed Interconnection Networks
HPI-DC 09 Fast-Response Multipath Routing Policy for High-Speed Interconnection Networks Diego Lugones, Daniel Franco, and Emilio Luque Leonardo Fialho Cluster 09 August 31 New Orleans, USA Outline Scope
More informationHomework Assignment #1: Topology Kelly Shaw
EE482 Advanced Computer Organization Spring 2001 Professor W. J. Dally Homework Assignment #1: Topology Kelly Shaw As we have not discussed routing or flow control yet, throughout this problem set assume
More informationMohammad Hossein Manshaei 1393
Mohammad Hossein Manshaei manshaei@gmail.com 1393 Voice and Video over IP Slides derived from those available on the Web site of the book Computer Networking, by Kurose and Ross, PEARSON 2 Multimedia networking:
More informationBasics (cont.) Characteristics of data communication technologies OSI-Model
48 Basics (cont.) Characteristics of data communication technologies OSI-Model Topologies Packet switching / Circuit switching Medium Access Control (MAC) mechanisms Coding Quality of Service (QoS) 49
More informationA Thermal-aware Application specific Routing Algorithm for Network-on-chip Design
A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design Zhi-Liang Qian and Chi-Ying Tsui VLSI Research Laboratory Department of Electronic and Computer Engineering The Hong Kong
More informationLoad Dynamix Enterprise 5.2
DATASHEET Load Dynamix Enterprise 5.2 Storage performance analytics for comprehensive workload insight Load DynamiX Enterprise software is the industry s only automated workload acquisition, workload analysis,
More informationFastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-cost High-performance Soft NoCs
1/29 FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-cost High-performance Soft NoCs Nachiket Kapre + Tushar Krishna nachiket@uwaterloo.ca, tushar@ece.gatech.edu 2/29 Claim FPGA overlay NoCs
More informationWhy Shaping Traffic at the Sender is Important. By Chuck Meyer, CTO, Production December 2017
Why Shaping Traffic at the Sender is Important By Chuck Meyer, CTO, Production December 2017 It s human nature to want to utilize a resource or tool to its fullest capacity. So, it stands to reason that
More informationUnit 2 Packet Switching Networks - II
Unit 2 Packet Switching Networks - II Dijkstra Algorithm: Finding shortest path Algorithm for finding shortest paths N: set of nodes for which shortest path already found Initialization: (Start with source
More informationWHITE PAPER. Latency & Jitter WHITE PAPER OVERVIEW
Latency & Jitter In Networking Performance Evaluation OVERVIEW Latency and jitter are two key measurement parameters when evaluating and benchmarking the performance of a network, system or device. Different
More informationModule objectives. Integrated services. Support for real-time applications. Real-time flows and the current Internet protocols
Integrated services Reading: S. Keshav, An Engineering Approach to Computer Networking, chapters 6, 9 and 4 Module objectives Learn and understand about: Support for real-time applications: network-layer
More informationAchieving Distributed Buffering in Multi-path Routing using Fair Allocation
Achieving Distributed Buffering in Multi-path Routing using Fair Allocation Ali Al-Dhaher, Tricha Anjali Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago, Illinois
More informationReal-Time Mixed-Criticality Wormhole Networks
eal-time Mixed-Criticality Wormhole Networks Leandro Soares Indrusiak eal-time Systems Group Department of Computer Science University of York United Kingdom eal-time Systems Group 1 Outline Wormhole Networks
More informationConquering Memory Bandwidth Challenges in High-Performance SoCs
Conquering Memory Bandwidth Challenges in High-Performance SoCs ABSTRACT High end System on Chip (SoC) architectures consist of tens of processing engines. In SoCs targeted at high performance computing
More informationPromoting the Use of End-to-End Congestion Control in the Internet
Promoting the Use of End-to-End Congestion Control in the Internet Sally Floyd and Kevin Fall IEEE/ACM Transactions on Networking May 1999 ACN: TCP Friendly 1 Outline The problem of Unresponsive Flows
More informationCombining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing?
Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing? J. Flich 1,P.López 1, M. P. Malumbres 1, J. Duato 1, and T. Rokicki 2 1 Dpto. Informática
More informationA closer look at network structure:
T1: Introduction 1.1 What is computer network? Examples of computer network The Internet Network structure: edge and core 1.2 Why computer networks 1.3 The way networks work 1.4 Performance metrics: Delay,
More informationA Predictable Communication Scheme for Embedded Multiprocessor Systems
A Predictable Communication Scheme for Embedded Multiprocessor Systems Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici Ecole Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland Email:
More informationTransaction Level Model Simulator for NoC-based MPSoC Platform
Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits & Systems, Hangzhou, China, April 15-17, 27 17 Transaction Level Model Simulator for NoC-based MPSoC Platform
More informationComparison of Shaping and Buffering for Video Transmission
Comparison of Shaping and Buffering for Video Transmission György Dán and Viktória Fodor Royal Institute of Technology, Department of Microelectronics and Information Technology P.O.Box Electrum 229, SE-16440
More informationTopologies. Maurizio Palesi. Maurizio Palesi 1
Topologies Maurizio Palesi Maurizio Palesi 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and
More informationChapter 1. Introduction
Chapter 1 Introduction In a packet-switched network, packets are buffered when they cannot be processed or transmitted at the rate they arrive. There are three main reasons that a router, with generic
More informationModelling a Video-on-Demand Service over an Interconnected LAN and ATM Networks
Modelling a Video-on-Demand Service over an Interconnected LAN and ATM Networks Kok Soon Thia and Chen Khong Tham Dept of Electrical Engineering National University of Singapore Tel: (65) 874-5095 Fax:
More informationNetwork on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN
Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN Multi Core Chips No more single processor systems High computational power requirements Increasing clock frequency increases power dissipation
More informationMinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems
MinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh Abstract The success of an electronic system in a System-on- Chip is highly
More informationQuality of Service (QoS)
Quality of Service (QoS) A note on the use of these ppt slides: We re making these slides freely available to all (faculty, students, readers). They re in PowerPoint form so you can add, modify, and delete
More informationSELECTION OF METRICS (CONT) Gaia Maselli
SELECTION OF METRICS (CONT) Gaia Maselli maselli@di.uniroma1.it Computer Network Performance 2 Selecting performance metrics Computer Network Performance 3 Selecting performance metrics speed Individual
More informationIEEE Time-Sensitive Networking (TSN)
IEEE 802.1 Time-Sensitive Networking (TSN) Norman Finn, IEEE 802.1CB, IEEE 802.1CS Editor Huawei Technologies Co. Ltd norman.finn@mail01.huawei.com Geneva, 27 January, 2018 Before We Start This presentation
More informationThomas Moscibroda Microsoft Research. Onur Mutlu CMU
Thomas Moscibroda Microsoft Research Onur Mutlu CMU CPU+L1 CPU+L1 CPU+L1 CPU+L1 Multi-core Chip Cache -Bank Cache -Bank Cache -Bank Cache -Bank CPU+L1 CPU+L1 CPU+L1 CPU+L1 Accelerator, etc Cache -Bank
More informationChapter 8. Network Troubleshooting. Part II
Chapter 8 Network Troubleshooting Part II CCNA4-1 Chapter 8-2 Network Troubleshooting Review of WAN Communications CCNA4-2 Chapter 8-2 WAN Communications Function at the lower three layers of the OSI model.
More informationDesign and Implementation of AXI-based Network-on-Chip Systems for Flow Regulation. Jiayi Zhang September 2009
TRITA-ICT-EX-29:157 Master Thesis in Electronic System Design Design and Implementation of AXI-based Network-on-Chip Systems for Flow Regulation Jiayi Zhang September 29 Supervisor: Examiner: Dr. Zhonghai
More informationChapter 2 Designing Crossbar Based Systems
Chapter 2 Designing Crossbar Based Systems Over the last decade, the communication architecture of SoCs has evolved from single shared bus systems to multi-bus systems. Today, state-of-the-art bus based
More informationOpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April
More informationArista 7050X, 7050X2, 7250X and 7300 Series Performance Validation
Arista 7050X, 7050X2, 7250X and 7300 Series Performance Validation Arista Networks was founded to deliver software driven cloud networking solutions for large datacenter and highperformance computing environments.
More informationBROADBAND AND HIGH SPEED NETWORKS
BROADBAND AND HIGH SPEED NETWORKS SWITCHING A switch is a mechanism that allows us to interconnect links to form a larger network. A switch is a multi-input, multi-output device, which transfers packets
More informationBasic Switch Organization
NOC Routing 1 Basic Switch Organization 2 Basic Switch Organization Link Controller Used for coordinating the flow of messages across the physical link of two adjacent switches 3 Basic Switch Organization
More informationMatching Information Network Reliability to Utility Grid Reliability
The Mandate of Utility Grid Uptime In the world of "five nines" reliability mandated for electric utilities, network continuity is allimportant. IT managers responsible for the IP network infrastructure
More informationCONGESTION CONTROL BY USING A BUFFERED OMEGA NETWORK
IADIS International Conference on Applied Computing CONGESTION CONTROL BY USING A BUFFERED OMEGA NETWORK Ahmad.H. ALqerem Dept. of Comp. Science ZPU Zarka Private University Zarka Jordan ABSTRACT Omega
More informationAn Approach for Enhanced Performance of Packet Transmission over Packet Switched Network
ISSN (e): 2250 3005 Volume, 06 Issue, 04 April 2016 International Journal of Computational Engineering Research (IJCER) An Approach for Enhanced Performance of Packet Transmission over Packet Switched
More informationMinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect Chris Fallin, Greg Nazario, Xiangyao Yu*, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu Carnegie Mellon University *CMU
More informationHigh Performance Interconnect and NoC Router Design
High Performance Interconnect and NoC Router Design Brinda M M.E Student, Dept. of ECE (VLSI Design) K.Ramakrishnan College of Technology Samayapuram, Trichy 621 112 brinda18th@gmail.com Devipoonguzhali
More informationPriority Traffic CSCD 433/533. Advanced Networks Spring Lecture 21 Congestion Control and Queuing Strategies
CSCD 433/533 Priority Traffic Advanced Networks Spring 2016 Lecture 21 Congestion Control and Queuing Strategies 1 Topics Congestion Control and Resource Allocation Flows Types of Mechanisms Evaluation
More informationOn Packet Switched Networks for On-Chip Communication
On Packet Switched Networks for On-Chip Communication Embedded Systems Group Department of Electronics and Computer Engineering School of Engineering, Jönköping University Jönköping 1 Outline : Part 1
More informationLow-Power Interconnection Networks
Low-Power Interconnection Networks Li-Shiuan Peh Associate Professor EECS, CSAIL & MTL MIT 1 Moore s Law: Double the number of transistors on chip every 2 years 1970: Clock speed: 108kHz No. transistors:
More informationSkewed-Associative Caches: CS752 Final Project
Skewed-Associative Caches: CS752 Final Project Professor Sohi Corey Halpin Scot Kronenfeld Johannes Zeppenfeld 13 December 2002 Abstract As the gap between microprocessor performance and memory performance
More informationSTG-NoC: A Tool for Generating Energy Optimized Custom Built NoC Topology
STG-NoC: A Tool for Generating Energy Optimized Custom Built NoC Topology Surbhi Jain Naveen Choudhary Dharm Singh ABSTRACT Network on Chip (NoC) has emerged as a viable solution to the complex communication
More informationAdaptive Internet Data Centers
Abstract Adaptive Internet Data Centers Jerome Rolia, Sharad Singhal, Richard Friedrich Hewlett Packard Labs, Palo Alto, CA, USA {jar sharad richf}@hpl.hp.com Trends in Internet infrastructure indicate
More informationQoS-Enabled Video Streaming in Wireless Sensor Networks
QoS-Enabled Video Streaming in Wireless Sensor Networks S. Guo and T.D.C. Little Department of Electrical and Computer Engineering Boston University, Boston, MA 02215 {guosong, tdcl}@bu.edu MCL Technical
More informationBroadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms
IEEE High Performance Extreme Computing Conference (HPEC), 2017 Broadening the Exploration of the Design Space in Embedded Scalable Platforms Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca
More informationPerformance Characterization, Prediction, and Optimization for Heterogeneous Systems with Multi-Level Memory Interference
The 2017 IEEE International Symposium on Workload Characterization Performance Characterization, Prediction, and Optimization for Heterogeneous Systems with Multi-Level Memory Interference Shin-Ying Lee
More informationSwitching Architectures for Cloud Network Designs
Switching Architectures for Cloud Network Designs Networks today require predictable performance and are much more aware of application flows than traditional networks with static addressing of devices.
More informationLecture 13: Interconnection Networks. Topics: lots of background, recent innovations for power and performance
Lecture 13: Interconnection Networks Topics: lots of background, recent innovations for power and performance 1 Interconnection Networks Recall: fully connected network, arrays/rings, meshes/tori, trees,
More informationPerformance of Multihop Communications Using Logical Topologies on Optical Torus Networks
Performance of Multihop Communications Using Logical Topologies on Optical Torus Networks X. Yuan, R. Melhem and R. Gupta Department of Computer Science University of Pittsburgh Pittsburgh, PA 156 fxyuan,
More informationResource Control and Reservation
1 Resource Control and Reservation Resource Control and Reservation policing: hold sources to committed resources scheduling: isolate flows, guarantees resource reservation: establish flows 2 Usage parameter
More informationRSVP 1. Resource Control and Reservation
RSVP 1 Resource Control and Reservation RSVP 2 Resource Control and Reservation policing: hold sources to committed resources scheduling: isolate flows, guarantees resource reservation: establish flows
More informationLayer 3: Network Layer. 9. Mar INF-3190: Switching and Routing
Layer 3: Network Layer 9. Mar. 2005 1 INF-3190: Switching and Routing Network Layer Goal Enable data transfer from end system to end system End systems Several hops, (heterogeneous) subnetworks Compensate
More informationAdvanced Computer Networks
Advanced Computer Networks QoS in IP networks Prof. Andrzej Duda duda@imag.fr Contents QoS principles Traffic shaping leaky bucket token bucket Scheduling FIFO Fair queueing RED IntServ DiffServ http://duda.imag.fr
More informationComparative Study of blocking mechanisms for Packet Switched Omega Networks
Proceedings of the 6th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical Communications, Corfu Island, Greece, February 16-19, 2007 18 Comparative Study of blocking mechanisms for Packet
More informationChapter -5 QUALITY OF SERVICE (QOS) PLATFORM DESIGN FOR REAL TIME MULTIMEDIA APPLICATIONS
Chapter -5 QUALITY OF SERVICE (QOS) PLATFORM DESIGN FOR REAL TIME MULTIMEDIA APPLICATIONS Chapter 5 QUALITY OF SERVICE (QOS) PLATFORM DESIGN FOR REAL TIME MULTIMEDIA APPLICATIONS 5.1 Introduction For successful
More informationQuality of Service II
Quality of Service II Patrick J. Stockreisser p.j.stockreisser@cs.cardiff.ac.uk Lecture Outline Common QoS Approaches Best Effort Integrated Services Differentiated Services Integrated Services Integrated
More informationInternet Services & Protocols. Quality of Service Architecture
Department of Computer Science Institute for System Architecture, Chair for Computer Networks Internet Services & Protocols Quality of Service Architecture Dr.-Ing. Stephan Groß Room: INF 3099 E-Mail:
More informationSolace Message Routers and Cisco Ethernet Switches: Unified Infrastructure for Financial Services Middleware
Solace Message Routers and Cisco Ethernet Switches: Unified Infrastructure for Financial Services Middleware What You Will Learn The goal of zero latency in financial services has caused the creation of
More informationSoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology
SoC Design Lecture 13: NoC (Network-on-Chip) Department of Computer Engineering Sharif University of Technology Outline SoC Interconnect NoC Introduction NoC layers Typical NoC Router NoC Issues Switching
More information