Lecture 5: Router Architecture. CS 598: Advanced Internetworking Matthew Caesar February 8, 2011

Transcription

1 Lecture 5: Router Architecture CS 598: Advanced Internetworking Matthew Caesar February 8,

2 IP Router... A router consists A set of input interfaces at which packets arrive A se of output interfaces from which packets depart Router implements two main functions Forward packet to corresponding output interface Manage congestion 2

3 Generic Router Architecture Input and output interfaces are connected through a backplane A backplane can be implemented by Shared memory Low capacity routers (e.g., PCbased routers) Shared bus Medium capacity routers Point-to-point (switched) bus High capacity routers input interface Interconnection Medium (Backplane) output interface 3

4 Speedup C input/output link capacity R I maximum rate at which an input interface can send data into backplane R O maximum rate at which an output can read data from backplane B maximum aggregate backplane transfer rate Back-plane speedup: B/C Input speedup: R I /C Output speedup: R O /C C input interface Interconnection Medium (Backplane) R I B output interface R O C 4

5 Function division Input interfaces: Must perform packet forwarding need to know to which output interface to send packets May enqueue packets and perform scheduling Output interfaces: May enqueue packets and perform scheduling C input interface Interconnection Medium (Backplane) R I B output interface R O C 5

6 Three Router Architectures Output queued Input queued Combined Input-Output queued 6

7 Output Queued (OQ) Routers Only output interfaces store packets Advantages Easy to design algorithms: only one congestion point Disadvantages Requires an output speedup of N, where N is the number of interfaces not feasible input interface output interface Backplane R O C 7

8 Input Queueing (IQ) Routers Only input interfaces store packets Advantages Easy to built Store packets at inputs if contention at outputs Relatively easy to design algorithms Only one congestion point, but not output need to implement backpressure Disadvantages Hard to achieve utilization 1 (due to output contention, head-of-line blocking) However, theoretical and simulation results show that for realistic traffic an input/output speedup of 2 is enough to achieve utilizations close to 1 input interface output interface Backplane R O C 8

9 Combined Input-Output Queueing (CIOQ) Routers Both input and output interfaces store packets Advantages Easy to built Utilization 1 can be achieved with limited input/output speedup (<= 2) Disadvantages Harder to design algorithms Two congestion points Need to design flow control Note: results show that with a input/output speedup of 2, a CIOQ can emulate any workconserving OQ [G+98,SZ98] input interface output interface Backplane R O C 9

10 Generic Architecture of a High Speed Router Today Combined Input-Output Queued Architecture Input/output speedup <= 2 Input interface Perform packet forwarding (and classification) Output interface Perform packet (classification and) scheduling Backplane Point-to-point (switched) bus; speedup N Schedule packet transfer from input to output 10

11 Backplane Point-to-point switch allows to simultaneously transfer a packet between any two disjoint pairs of input-output interfaces Goal: come-up with a schedule that Meet flow QoS requirements Maximize router throughput Challenges: Address head-of-line blocking at inputs Resolve input/output speedups contention Avoid packet dropping at output if possible Note: packets are fragmented in fix sized cells (why?) at inputs and reassembled at outputs In Partridge et al, a cell is 64 B (what are the trade-offs?) 11

12 Head-of-line Blocking The cell at the head of an input queue cannot be transferred, thus blocking the following cells Cannot be transferred because is blocked by red cell Input 1 Input 2 Input 3 Cannot be transferred because output buffer full Output 1 Output 2 Output 3 12

13 Solution to Avoid Head-of-line Blocking Maintain at each input N virtual queues, i.e., one per output Input 1 Input 2 Output 1 Output 2 Output 3 Input 3 13

14 Cell transfer Schedule: Ideally: find the maximum number of input-output pairs such that: Example Resolve input/output contentions Avoid packet drops at outputs Packets meet their time constraints (e.g., deadlines), if any Assign cell preferences at inputs, e.g., their position in the input queue Assign cell preferences at outputs, e.g., based on packet deadlines, or the order in which cells would depart in a OQ router Match inputs and outputs based on their preferences Problem: Achieving a high quality matching complex, i.e., hard to do in constant time 14

15 Routing vs. Forwarding Routing: control plane Computing paths the packets will follow Routers talking amongst themselves Individual router creating a forwarding table Forwarding: data plane Directing a data packet to an outgoing link Individual router using a forwarding table 15

16 How the control and data planes work together (logical view) Update /8 Protocol daemon RIB /8 IF 2 Control Plane IF 1 IF 2 FIB /8 IF 2 Data Plane /8 Data packet

17 Physical layout of a high-end router data plane Route Processor control plane Line card Line card Line card Switching Fabric Line card Line card Line card 17

18 Routing vs. Forwarding Control plane s jobs include Route calculation Maintenance of routing table Execution of routing protocols On commercial routers, handled by special-purpose processor called route processor IP forwarding is per-packet processing 18 On high-end commercial routers, IP forwarding is distributed Most work is done by interface cards data plane Route Processor Switching Fabric control plane

19 Router Components On a PC router: Interconnection network is the PCI bus Interface cards are the NICs (e.g., Ethernet cards) All forwarding and routing is done on a commodity CPU On commercial routers: Interconnection network and interface cards are sophisticated, special-purpose hardware Packet forwarding oftend implemented in a custom ASIC Only routing (control plane) is done on the commodity CPU (route processor)

20 Slotted Chassis Large routers are built as a slotted chassis Interface cards are inserted in the slots Route processor is also inserted as a slot This simplifies repairs and upgrades of components E.g., hot-swapping of components

21 Evolution of router architectures Early routers were just general-purpose computers Today, high-performance routers resemble mini data centers Exploit parallelism Specialized hardware Until 1980s (1 st generation): standard computer Early 1990s (2 nd generation): delegate packet processing to interfaces Late 1990s (3 rd generation): distributed architecture Today: distributed across multiple racks 21

22 First generation routers This architecture is still used in low-end routers Arriving packets are copied to main memory via direct memory access (DMA) Interconnection network is a backplane (shared bus) All IP forwarding functions are performed by a commodity CPU Routing cache at processor can accelerate the routing table lookup Drawbacks: Forwarding performance is limited by the CPU Capacity of shared bus limits the number of interface cards that can be connected CPU Buffer Memory DMA DMA DMA Line Interface MAC Line Interface MAC Typically <0.5Gb/s aggregate capacity Off-chip buffer memory Line Interface MAC Shared bus 22

23 Second generation routers Bypasses memory bus with direct transfer over bus between line cards CPU Buffer Memory Moves forwarding decisions local to card to reduce CPU utilization DMA DMA DMA Line Card Local Buffer Memory Line Card Local Buffer Memory Line Card Local Buffer Memory Trap to CPU for slow operations MAC MAC MAC Typically <5Gb/s aggregate capacity 23

24 Speeding up the common case with a Fast path IP packet forwarding is complex But, vast majority of packets can be forwarded with simple algorithm Main idea: put common-case forwarding in hardware, trap to software on exceptions Example: BBN router had 85 instructions for fast-path code, which fits entirely in L1 cache Non-common cases handled by slow path: Route cache misses Errors (e.g., ICMP time exceeded) IP options Fragmented packets Multicast packets 24

25 Improving upon secondgeneration routers Control plane must remember lots of information (BGP attributes, etc.) But data plane only needs to know FIB Smaller, fixed-length attributes Idea: store FIB in hardware Going over the bus adds delay Idea: Cache FIB in line cards Send directly over bus to outbound line card 25

26 Improving upon secondgeneration routers Shared bus is a big bottleneck E.g., modern PCI bus (PCIx16) is only 32Gbit/sec (in theory) Almost-modern Cisco (XR 12416) is 320 Gbit/sec Ow! How do we get there? Idea: put a network inside the router Switched backplane for larger cross-section bandwidths 26

27 Third generation routers Replace bus with interconnection network (e.g., a crossbar switch) Distributed architecture: Line cards operate independently of one another independently of one another Line CPU Line Card Card Card No centralized processing for IP forwarding These routers can be scaled to many hundreds of interface cards and capacity of > 1 Tbit/sec Local Buffer Memory MAC Local Buffer Memory MAC 27

28 Switch Fabric: From Input to Output Data Hdr Header Processing Lookup Address Update Header 1 1 Queue Packet Address Table Buffer Memory Data Hdr Header Processing Lookup Update Address Header 2 2 Queue Packet Address Table Buffer Memory Header Processing Data Hdr N N Lookup Address Update Header Queue Packet Address Table Buffer Memory

29 Crossbars N input ports, N output ports One per line card, usually Every line card has its own forwarding table/classifier/etc --- removes CPU bottleneck Scheduler Decides which input/output port pairs to connect in a given time slot Often forward fixed-sized cells to avoid variable-length time slots Crossbar constraint If input i is connected to output j, no other input connected to j, no other output connected to i Scheduling is a bipartite matching 29

30 Data Plane Details: Checksum Takes too much time to verify checksum Increases forwarding time by 21% Take an optimistic approach: just incrementally update it Safe operation: if checksum was correct it remains correct If checksum bad, it will be anyway caught by endhost Note: IPv6 does not include a header checksum anyway! 30

31 Multi-chassis routers Multi-chassis router A single router that is a distributed collection of racks Scales to 322 Tbps, can replace an entire PoP 31

32 Why multi-chassis routers? ~ 40 routers per PoP (easily) in today s Intra-PoP architectures Connections between these routers require the same expensive line cards as inter-pop connections 32 Support forwarding tables, QoS, monitoring, configuration, MPLS Line cards are dominant cost of router, and racks often limited to sixteen 40 Gbps line cards Each connection appears as an adjacency in the routing protocol Increases IGP/iBGP control-plane overhead Increases complexity of scaling techniques such as route reflectors and summarization

33 Multi-chassis routers to the rescue Multi-chassis design: each line-card chassis has some fabric interface cards 33 Do not use line-card slots: instead uses a separate, smaller connection Do not need complex packet processing logic much cheaper than line cards Multi-chassis router acts as one router to the outside world Simplifies administration Reduces number of ibgp adjacencies and IGP nodes/links without resorting to complex scaling techniques However, now the multi-chassis router becomes a distributed system Interesting research topics Needs rethinking of router software (distributed and parallel) Needs high resilience (no external backup routers)

34 Matching Algorithms

35 Administrivia Lecture topics+outlines due today Next step: slide-based outline by 2/16 Put down the text for your slides (no graphics) Project topics due on 2/10 Send me a 1 paragraph description of your project, names of people in your group 35

36 What s so hard about IP packet forwarding? Back-of-the-envelope numbers Line cards can be 40 Gbps today (OC-768) Getting faster every year! To handle minimum-sized packets (~40b) 125 Mpps, or 8ns per packet Can use parallelism, but need to be careful about reordering For each packet, you must Do a routing lookup (where to send it) Schedule the crossbar Maybe buffer, maybe QoS, maybe ACLs, 36

37 Routing lookups Routing tables: 200,000 to 1M entries Router must be able to handle routing table loads 5-10 years hence How can we store routing state? What kind of memory to use? How can we quickly lookup with increasingly large routing tables? 37

38 Memory technologies Technology Single chip density $/MByte Access speed Watts/ chip Dynamic RAM (DRAM) cheap, slow Static RAM (SRAM) expensive, fast, a bit higher heat/power Ternary Content Addressable Memory (TCAM) very expensive, very high heat/power, very fast (does parallel lookups in hardware) 64 MB $0.50- $ ns 0.5-2W 4 MB $5-$8 4-8ns 1-3W 1 MB $200-$ ns 15-30W Vendors moved from DRAM (1980s) to SRAM (1990s) to TCAM (2000s) Vendors are now moving back to SRAM and parallel banks of DRAM due to power/heat 38

39 Fixed-Length Matching Algorithms

40 Ethernet Switch Lookup frame DA in forwarding table. If known, forward to correct port. If unknown, broadcast to all ports. Learn SA of incoming frame. Forward frame to outgoing interface. Transmit frame onto link. How to do this quickly? Need to determine next hop quickly Would like to do so without reducing line rates 40

41 Why Ethernet needs wire-speed forwarding Scenario: Bridge has a 500 packet buffer Link rate: 1 packet/ms Lookup rate: 0.5 packet/ms A sends 1000 packets to B A sends 10 packets to C What happens to C s packets? What would happen if this Bridge was a Router? Need wirespeed forwarding A C Bridge A B C 41

42 Inside a switch Ethernet chip Ethernet 1 Processor Lookup engine Ethernet 2 Packet/lookup memory Ethernet chip Packet received from upper Ethernet Ethernet chip extracts source address S, stored in shared memory, in receive queue Ethernet chips set in promiscuous mode Extracts destination address D, given to lookup engine 42

43 F0:4D:A2:3A:31:9C Eth 1 00:21:9B:77:F2:65 Eth 2 8B:01:54:A2:78:9C Eth 1 00:0C:F1:56:98:AD Eth 1 00:B0:D0:86:BB:F7 Eth 2 00:A0:C9:14:C8:29 Eth 2 90:03:BA:26:01:B0 Eth 2 00:0C:29:A8:D0:FA Eth 1 00:10:7F:00:0D:B7 Lookup Processor Eth 2 engine Inside a switch Ethernet chip Packet/lookup memory Ethernet 1 Ethernet 2 Ethernet chip Lookup engine looks up D in database stored in memory If destination is on upper Ethernet: set packet buffer pointer to free queue If destination is on lower Ethernet: set packet buffer pointer to transmit queue of the lower Ethernet How to do the lookup quickly? 43

44 Problem overview 90:03:BA:26:01:B0 F0:4D:A2:3A:31:9C Eth 1 00:21:9B:77:F2:65 Eth 2 8B:01:54:A2:78:9C Eth 1 00:0C:F1:56:98:AD Eth 1 00:B0:D0:86:BB:F7 Eth 2 Eth 2 00:A0:C9:14:C8:29 Eth 2 90:03:BA:26:01:B0 Eth 2 00:0C:29:A8:D0:FA Eth 1 00:10:7F:00:0D:B7 Eth 2 Goal: given address, look up outbound interface Do this quickly (few instructions/low circuit complexity) Linear search too low 44

45 Idea #1: binary search 90:03:BA:26:01:B0 F0:4D:A2:3A:31:9C 00:0C:F1:56:98:AD Eth 1 00:10:7F:00:0D:B7 00:21:9B:77:F2:65 Eth 2 8B:01:54:A2:78:9C 00:21:9B:77:F2:65 Eth 21 00:B0:D0:86:BB:F7 00:0C:F1:56:98:AD Eth 12 00:B0:D0:86:BB:F7 00:A0:C9:14:C8:29 Eth 2 Eth 2 00:0C:29:A8:D0:FA 00:A0:C9:14:C8:29 Eth 21 8B:01:54:A2:78:9C 90:03:BA:26:01:B0 Eth 21 00:0C:29:A8:D0:FA 90:03:BA:26:01:B0 Eth 21 F0:4D:A2:3A:31:9C 00:10:7F:00:0D:B7 Eth 21 Put all destinations in a list, sort them, binary search Problem: logarithmic time 45

46 8B:01:54:A2:78:9C F0:4D:A2:3A:31:9C 00:10:7F:00:0D:B7 Improvement: Parallel Binary search 00:A0:C9:14:C8:29 00:21:9B:77:F2:65 8B:01:54:A2:78:9C 00:10:7F:00:0D:B7 00:B0:D0:86:BB:F7 00:0C:29:A8:D0:FA 90:03:BA:26:01:B0 00:0C:F1:56:98:AD 00:10:7F:00:0D:B7 00:21:9B:77:F2:65 00:B0:D0:86:BB:F7 00:A0:C9:14:C8:29 00:0C:29:A8:D0:FA 8B:01:54:A2:78:9C 90:03:BA:26:01:B0 F0:4D:A2:3A:31:9C Packets still have O(log n) delay, but can process O(log n) packets in parallel O(1) 46

47 8B:01:54:A2:78:9C F0:4D:A2:3A:31:9C 00:10:7F:00:0D:B7 Improvement: Parallel Binary search 00:A0:C9:14:C8:29 00:21:9B:77:F2:65 8B:01:54:A2:78:9C 00:10:7F:00:0D:B7 00:B0:D0:86:BB:F7 00:0C:29:A8:D0:FA 90:03:BA:26:01:B0 00:0C:F1:56:98:AD 00:10:7F:00:0D:B7 00:21:9B:77:F2:65 00:B0:D0:86:BB:F7 00:A0:C9:14:C8:29 00:0C:29:A8:D0:FA 8B:01:54:A2:78:9C 90:03:BA:26:01:B0 F0:4D:A2:3A:31:9C Packets still have O(log n) delay, but can process O(log n) packets in parallel O(1) 47

48 Idea #2: hashing keys F0:4D:A2:3A:31:9C 00:21:9B:77:F2:65 8B:01:54:A2:78:9C 00:0C:F1:56:98:AD 00:B0:D0:86:BB:F7 00:A0:C9:14:C8:29 90:03:BA:26:01:B0 00:0C:29:A8:D0:FA 00:10:7F:00:0D:B7 function hashes bins 8B:01:54:A2:78:9C F0:4D:A2:3A:31:9C 00:0C:29:A8:D0:FA 90:03:BA:26:01:B0 00:10:7F:00:0D:B7 00:21:9B:77:F2:65 90:03:BA:26:01:B0 00:B0:D0:86:BB:F7 00:A0:C9:14:C8:29 00:0C:F1:56:98:AD Hash key=destination, value=interface pairs Lookup in O(1) with hash Problem: chaining (not really O(1))

49 Improvement: Perfect hashing keys F0:4D:A2:3A:31:9C 00:21:9B:77:F2:65 8B:01:54:A2:78:9C 00:0C:F1:56:98:AD 00:B0:D0:86:BB:F7 00:A0:C9:14:C8:29 parameter hashes bins 8B:01:54:A2:78:9C F0:4D:A2:3A:31:9C 00:0C:29:A8:D0:FA 90:03:BA:26:01:B0 00:10:7F:00:0D:B :03:BA:26:01:B0 90:03:BA:26:01:B0 00:B0:D0:86:BB:F7 00:0C:29:A8:D0:FA 00:A0:C9:14:C8: :0C:F1:56:98:AD 00:10:7F:00:0D:B7 Perfect hashing: find a hash function that maps perfectly with no collisions Gigaswitch approach Use a parameterized hash function Precompute hash function to bound worst case number of collisions :21:9B:77:F2:65 49

50 Variable-Length Matching Algorithms

51 Longest Prefix Match Not just one entry that matches a destination /24 and /16 Which one to use for ? By convention, Internet routers choose the longest (most-specific) match Need variable prefix match algorithms Several methods 51

52 Method 1: Trie Sample Database P1=10* P2=111* P3=11001* P4=1* P5=0* P6=1000* P7=100000* P8= * Trie Tree of (left ptr, right ptr) data structures May be stored in SRAM/DRAM Lookup performed by traversing sequence of pointers Lookup time O(log N) where N is # prefixes 52

53 Improvement 1: Skip Counts and Path Compression Removing one-way branches ensures # of trie nodes is at most twice # of prefixes Using a skip count requires exact match at end and backtracking on failure path compression is simpler Main idea behind Patricia Tries 53

54 Improvement 2: Multi-way tree 16-ary Search Trie 0000, ptr 1111, ptr 0000, , ptr 0000, , ptr Doing multiple comparisons per cycle accelerates lookup Can do this for free to the width of CPU word (modern CPUs process multiple bits per cycle) But increases wasted space (more unused pointers) 54

55 Improvement 2: Multi-way tree E w = D L N D + D i (( 1 D i 1 ) N ( 1 D 1 i ) N ) D L L 1 i = 1 L 1 E n = 1 + D L N D + D i D i 1 ( 1 D i 1 ) N D L i = 1 Where: D = Degree of tree L = Number of layers/references N = Number of entries in table E n = Expected number of nodes E w = Expected amount of wasted memory Degree of # Mem # Nodes Total Memory Fraction Tree References (x10 6 ) (Mbytes) Wasted (%) Table produced from 2 15 randomly generated 48-bit addresses 55

56 Method 2: Lookups in Hardware Num mber Prefix length Observation: most prefixes are /24 or shorter So, just store a big 2^24 table with next hop for each prefix Nonexistant prefixes just leave that entry empty 56

57 Method 2: Lookups in Hardware Prefixes up to 24-bits 2 24 = 16M entries Next Hop Next Hop

58 Method 2: Lookups in Hardware Prefixes up to 24-bits Next Hop Pointer 8 offset base Prefixes above 24-bits Next Hop Next Hop 58

59 Method 2: Lookups in Hardware Advantages Very fast lookups 20 Mpps with 50ns DRAM Easy to implement in hardware Disadvantages Large memory required Performance depends on prefix length distribution 59

60 Method 3: Ternary CAMs Associative Memory Value Mask Next hop Lookup Value IF IF IF 4 Next Hop IF IF 2 Selector Content Addressable Hardware searches entire memory to find supplied value Similar interface to hash table Ternary : memory can be in three states True, false, don t care Hardware to treat don t care as wildcard match

61 Classification Algorithms

62 Providing Value-Added Services Differentiated services Regard traffic from AS#33 as `platinum-grade Access Control Lists Deny udp host eq snmp Committed Access Rate Rate limit WWW traffic from sub-interface#739 to 10Mbps Policy-based Routing Route all voice traffic through the ATM network Peering Arrangements Restrict the total amount of traffic of precedence 7 from MAC address N to 20 Mbps between 10 am and 5pm Accounting and Billing Generate hourly reports of traffic from MAC address M Need to address the Flow Classification problem 62

63 Flow Classification H E A D E R Incoming Packet Forwarding Engine Flow Classification Policy Database Predicate Action Flow Index 63

64 A Packet Classifier Field 1 Field 2 Field k Action Rule / /32 Rule / /16 Udp A1 Tcp A2 Rule N / /32 Any An Given a classifier, find the action associated with the highest priority rule (here, the lowest numbered rule) matching an incoming packet. 64

65 Geometric Interpretation in 2D Field #1 Field #2 Data R7 R6 P2 P1 Field #2 R3 e.g. (144.24/16, 64/24) e.g. ( , *) R5 R4 R2 R1 Field #1 65

66 Approach #1: Linear search Build linked list of all classification rules Possibly sorted in order of decreasing priorities For each arriving packet, evaluate each rule until match is found Pros: simple and storage efficient Cons: classification time grows linearly with number of rules Variant: build FSM of rules (pattern matching) 66

67 Approach #2: Ternary CAMs Similar to TCAM use in prefix matching Need wider than 32-bit array, typically bits Ranges expressed as don t cares below a particular bit Done for each field Pros: O(1) lookup time, simple Cons: heat, power, cost, etc. Power for a TCAM row increases proportionally to 67 its width

68 Approach #3: Hierarchical trie F2 F1 Recursively build d-dimensional radix trie Trie for first field, attach sub-tries to trie s leaves for subfield, repeat For N-bit rules, d dimensions, W-bit wide dimensions: Storage complexity: O(NdW) Lookup complexity: O(W^d) 68

69 Approach #4: Set-pruning tries F2 F1 Push rules down the hierarchical trie Eliminates need for recursive lookups For N-bit rules, d dimensions, W-bit wide dimensions: Storage complexity: O(dWN^d) Lookup complexity: O(dW) 69

70 Approach #5: Crossproducting Compute separate 1-dimensional range lookups for each dimension For N-bit rules, d dimensions, W-bit wide dimensions: Storage complexity: O(N^d) Lookup complexity: O(dW) 70

71 Other proposed schemes 71